[PATCH v3 1/1] AArch64: Relax regexps in tests to let them pass with -fweb

[Christopher Bazley via Sourceware Forge]

From: Christopher Bazley <chris.baz...@arm.com>

The -fweb option changes the way that GCC allocates
registers.  -fweb is not enabled by default, so we
have never previously noticed that some AArch64 tests
have unreasonably strict expectations about register
allocation.  This patch relaxes those expectations.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/ffs.c: Relax test expectations.
        * gcc.target/aarch64/frecpe_1.c: As above.
        * gcc.target/aarch64/frecpe_2.c: As above.
---
 gcc/testsuite/gcc.target/aarch64/ffs.c      | 20 ++++++++++----------
 gcc/testsuite/gcc.target/aarch64/frecpe_1.c |  2 +-
 gcc/testsuite/gcc.target/aarch64/frecpe_2.c |  4 ++--
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/gcc/testsuite/gcc.target/aarch64/ffs.c 
b/gcc/testsuite/gcc.target/aarch64/ffs.c
index a303bee5fd47..59e55eefcc0d 100644
--- a/gcc/testsuite/gcc.target/aarch64/ffs.c
+++ b/gcc/testsuite/gcc.target/aarch64/ffs.c
@@ -9,9 +9,9 @@
 /*
 ** ffsw1:
 **     cmp     w1, 0
-**     rbit    w0, w1
-**     clz     w0, w0
-**     csinc   w0, wzr, w0, eq
+**     rbit    (w[0-9]+), w1
+**     clz     (w[0-9]+), \1
+**     csinc   w0, wzr, \2, eq
 **     ret
 */
 
@@ -23,9 +23,9 @@ int ffsw1 (int y, uint32_t x)
 /*
 ** ffsx1:
 **     cmp     x1, 0
-**     rbit    x0, x1
-**     clz     x0, x0
-**     csinc   x0, xzr, x0, eq
+**     rbit    (x[0-9]+), x1
+**     clz     (x[0-9]+), \1
+**     csinc   x0, xzr, \2, eq
 **     ret
 */
 
@@ -39,8 +39,8 @@ int ffsx1 (int y, uint64_t x)
 /*
 ** ffsw2:
 **     cmp     w1, 0
-**     ctz     w0, w1
-**     csinc   w0, wzr, w0, eq
+**     ctz     (w[0-9]+), w1
+**     csinc   w0, wzr, \1, eq
 **     ret
 */
 
@@ -52,8 +52,8 @@ int ffsw2 (int y, uint32_t x)
 /*
 ** ffsx2:
 **     cmp     x1, 0
-**     ctz     x0, x1
-**     csinc   x0, xzr, x0, eq
+**     ctz     (x[0-9]+), x1
+**     csinc   x0, xzr, \1, eq
 **     ret
 */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/frecpe_1.c 
b/gcc/testsuite/gcc.target/aarch64/frecpe_1.c
index e79f80d3ead5..321d820a0f32 100644
--- a/gcc/testsuite/gcc.target/aarch64/frecpe_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/frecpe_1.c
@@ -15,4 +15,4 @@ f2 (double x)
   return 1 / x;
 }
 
-/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), 
\1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\td0, \1, \2\n} } } */
+/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), 
\1, d0\n\tfmul\t(d[0-9]+), \1, \2\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\td0, \3, 
\4\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/frecpe_2.c 
b/gcc/testsuite/gcc.target/aarch64/frecpe_2.c
index 233817c26b26..907181d53e7e 100644
--- a/gcc/testsuite/gcc.target/aarch64/frecpe_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/frecpe_2.c
@@ -7,7 +7,7 @@ f1 (float x, float y)
   return y / x;
 }
 
-/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), 
\1, s0\n\tfmul\t\1, \1, s1\n\tfmul\ts0, \1, \2\n} } } */
+/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), 
\1, s0\n\tfmul\t(s[0-9]+), \1, s1\n\tfmul\ts0, \3, \2\n} } } */
 
 double
 f2 (double x, double y)
@@ -15,4 +15,4 @@ f2 (double x, double y)
   return y / x;
 }
 
-/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), 
\1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\t\1, \1, 
d1\n\tfmul\td0, \1, \2\n} } } */
+/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), 
\1, d0\n\tfmul\t(d[0-9]+), \1, \2\n\tfrecps\t(d[0-9]+), \3, 
d0\n\tfmul\t(d[0-9]+), \3, d1\n\tfmul\td0, \5, \4\n} } } */
-- 
2.54.0