On Mon, 10 Aug 2026, [email protected] wrote:
> From: Kyrylo Tkachov <[email protected]>
>
> The widen_ssum and widen_usum optabs are only ever used to implement the
> accumulator update of a reduction that the vectorizer has already
> established may be reassociated. The name suggests a plain lane preserving
> widening add, which is a different and useful operation that a target may
> want to expose separately.
>
> Rename the optabs and the standard pattern names to reduc_widen_ssum and
> reduc_widen_usum, which puts them alongside the other reduc_* names and
> leaves widen_[us]sum free for a lane preserving pattern. The internal
> optab identifiers become reduc_widen_ssum_optab and reduc_widen_usum_optab
> rather than keeping the reversed reduc_ssum_widen_optab form of the old
> ssum_widen_optab and usum_widen_optab, so that the identifier now reads the
> same way as the pattern name it generates.
>
> This is a pure rename. No pattern gains or loses a mode, so generated code
> is unchanged.
>
> Bootstrapped and tested on aarch64-none-linux-gnu and confirmed that each of
> the targets affected by the renaming builds.
>
> Ok for trunk?
OK.
Thanks,
Richard.
> Thanks,
> Kyrill
>
> gcc/ChangeLog:
>
> * optabs.def (ssum_widen_optab): Rename to ...
> (reduc_widen_ssum_optab): ... this. Rename the pattern from
> widen_ssum$a$b3 to reduc_widen_ssum$a$b3.
> (usum_widen_optab): Rename to ...
> (reduc_widen_usum_optab): ... this. Rename the pattern from
> widen_usum$a$b3 to reduc_widen_usum$a$b3.
> * optabs-tree.cc (optab_for_tree_code): Update for the renamed
> optabs.
> * doc/md.texi (widen_ssum@var{n}@var{m}3): Rename to ...
> (reduc_widen_ssum@var{n}@var{m}3): ... this.
> (widen_usum@var{n}@var{m}3): Rename to ...
> (reduc_widen_usum@var{n}@var{m}3): ... this.
> * config/aarch64/aarch64-simd.md (widen_ssum<Vdblw><mode>3): Rename
> to ...
> (reduc_widen_ssum<Vdblw><mode>3): ... this.
> (widen_ssum<Vwide><mode>3): Rename to ...
> (reduc_widen_ssum<Vwide><mode>3): ... this.
> (widen_usum<Vdblw><mode>3): Rename to ...
> (reduc_widen_usum<Vdblw><mode>3): ... this.
> (widen_usum<Vwide><mode>3): Rename to ...
> (reduc_widen_usum<Vwide><mode>3): ... this.
> (widen_ssum<mode><vsi2qi>3): Rename to ...
> (reduc_widen_ssum<mode><vsi2qi>3): ... this.
> (widen_usum<mode><vsi2qi>3): Rename to ...
> (reduc_widen_usum<mode><vsi2qi>3): ... this.
> * config/aarch64/aarch64-sve.md (widen_<sur>sum<mode><vsi2qi>3):
> Rename to ...
> (reduc_widen_<sur>sum<mode><vsi2qi>3): ... this.
> * config/aarch64/aarch64-sve2.md (widen_ssum<mode><Vnarrow>3): Rename
> to ...
> (reduc_widen_ssum<mode><Vnarrow>3): ... this.
> (widen_usum<mode><Vnarrow>3): Rename to ...
> (reduc_widen_usum<mode><Vnarrow>3): ... this.
> * config/arm/neon.md (widen_ssum<v_double_width><mode>3): Rename
> to ...
> (reduc_widen_ssum<v_double_width><mode>3): ... this.
> (widen_ssum<V_widen_l><mode>3): Rename to ...
> (reduc_widen_ssum<V_widen_l><mode>3): ... this.
> (widen_usum<v_double_width><mode>3): Rename to ...
> (reduc_widen_usum<v_double_width><mode>3): ... this.
> (widen_usum<V_widen_l><mode>3): Rename to ...
> (reduc_widen_usum<V_widen_l><mode>3): ... this.
> * config/ia64/vect.md (widen_usumv4hiv8qi3): Rename to ...
> (reduc_widen_usumv4hiv8qi3): ... this.
> (widen_usumv2siv4hi3): Rename to ...
> (reduc_widen_usumv2siv4hi3): ... this.
> (widen_ssumv4hiv8qi3): Rename to ...
> (reduc_widen_ssumv4hiv8qi3): ... this.
> (widen_ssumv2siv4hi3): Rename to ...
> (reduc_widen_ssumv2siv4hi3): ... this.
> * config/rs6000/altivec.md (widen_usumv4si<mode>3): Rename to ...
> (reduc_widen_usumv4si<mode>3): ... this.
> (widen_ssumv4siv16qi3): Rename to ...
> (reduc_widen_ssumv4siv16qi3): ... this.
> (widen_ssumv4siv8hi3): Rename to ...
> (reduc_widen_ssumv4siv8hi3): ... this.
>
> Signed-off-by: Kyrylo Tkachov <[email protected]>
> ---
> gcc/config/aarch64/aarch64-simd.md | 12 ++++++------
> gcc/config/aarch64/aarch64-sve.md | 4 ++--
> gcc/config/aarch64/aarch64-sve2.md | 8 ++++----
> gcc/config/arm/neon.md | 8 ++++----
> gcc/config/ia64/vect.md | 8 ++++----
> gcc/config/rs6000/altivec.md | 6 +++---
> gcc/doc/md.texi | 8 ++++----
> gcc/optabs-tree.cc | 3 ++-
> gcc/optabs.def | 4 ++--
> 9 files changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index aa6c1fa0735..39569fbe4c9 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -5283,7 +5283,7 @@
>
> ;; <su><addsub>w<q>.
>
> -(define_expand "widen_ssum<Vdblw><mode>3"
> +(define_expand "reduc_widen_ssum<Vdblw><mode>3"
> [(set (match_operand:<VDBLW> 0 "register_operand")
> (plus:<VDBLW> (sign_extend:<VDBLW>
> (match_operand:VQW 1 "register_operand"))
> @@ -5300,7 +5300,7 @@
> }
> )
>
> -(define_expand "widen_ssum<Vwide><mode>3"
> +(define_expand "reduc_widen_ssum<Vwide><mode>3"
> [(set (match_operand:<VWIDE> 0 "register_operand")
> (plus:<VWIDE> (sign_extend:<VWIDE>
> (match_operand:VD_BHSI 1 "register_operand"))
> @@ -5311,7 +5311,7 @@
> DONE;
> })
>
> -(define_expand "widen_usum<Vdblw><mode>3"
> +(define_expand "reduc_widen_usum<Vdblw><mode>3"
> [(set (match_operand:<VDBLW> 0 "register_operand")
> (plus:<VDBLW> (zero_extend:<VDBLW>
> (match_operand:VQW 1 "register_operand"))
> @@ -5328,7 +5328,7 @@
> }
> )
>
> -(define_expand "widen_usum<Vwide><mode>3"
> +(define_expand "reduc_widen_usum<Vwide><mode>3"
> [(set (match_operand:<VWIDE> 0 "register_operand")
> (plus:<VWIDE> (zero_extend:<VWIDE>
> (match_operand:VD_BHSI 1 "register_operand"))
> @@ -5339,7 +5339,7 @@
> DONE;
> })
>
> -(define_expand "widen_ssum<mode><vsi2qi>3"
> +(define_expand "reduc_widen_ssum<mode><vsi2qi>3"
> [(set (match_operand:VS 0 "register_operand")
> (plus:VS (sign_extend:VS
> (match_operand:<VSI2QI> 1 "register_operand"))
> @@ -5355,7 +5355,7 @@
>
> ;; Use dot product to perform double widening sum reductions by
> ;; changing += a into += (a * 1). i.e. we seed the multiplication with 1.
> -(define_expand "widen_usum<mode><vsi2qi>3"
> +(define_expand "reduc_widen_usum<mode><vsi2qi>3"
> [(set (match_operand:VS 0 "register_operand")
> (plus:VS (zero_extend:VS
> (match_operand:<VSI2QI> 1 "register_operand"))
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index 5f9a19c42e9..7a5db18586f 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -7884,10 +7884,10 @@
> [(set_attr "sve_type" "sve_int_dot")]
> )
>
> -;; Define double widen_[su]sum as dotproduct
> +;; Define double reduc_widen_[su]sum as dotproduct
> ;; Use dot product to perform double widening sum reductions by
> ;; changing += a into += (a * 1). i.e. we seed the multiplication with 1.
> -(define_expand "widen_<sur>sum<mode><vsi2qi>3"
> +(define_expand "reduc_widen_<sur>sum<mode><vsi2qi>3"
> [(set (match_operand:SVE_FULL_SDI 0 "register_operand")
> (plus:SVE_FULL_SDI
> (unspec:SVE_FULL_SDI
> diff --git a/gcc/config/aarch64/aarch64-sve2.md
> b/gcc/config/aarch64/aarch64-sve2.md
> index fe6aa65823d..4eeb96edcd5 100644
> --- a/gcc/config/aarch64/aarch64-sve2.md
> +++ b/gcc/config/aarch64/aarch64-sve2.md
> @@ -2563,8 +2563,8 @@
> [(set_attr "sve_type" "sve_int_general")]
> )
>
> -;; Define single step widening for widen_ssum using SADDWB and SADDWT
> -(define_expand "widen_ssum<mode><Vnarrow>3"
> +;; Define single step widening for reduc_widen_ssum using SADDWB and SADDWT
> +(define_expand "reduc_widen_ssum<mode><Vnarrow>3"
> [(set (match_operand:SVE_FULL_HSDI 0 "register_operand")
> (unspec:SVE_FULL_HSDI
> [(match_operand:SVE_FULL_HSDI 2 "register_operand")
> @@ -2590,8 +2590,8 @@
> }
> })
>
> -;; Define single step widening for widen_usum using UADDWB and UADDWT
> -(define_expand "widen_usum<mode><Vnarrow>3"
> +;; Define single step widening for reduc_widen_usum using UADDWB and UADDWT
> +(define_expand "reduc_widen_usum<mode><Vnarrow>3"
> [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w")
> (unspec:SVE_FULL_HSDI
> [(match_operand:SVE_FULL_HSDI 2 "register_operand" "w")
> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
> index 4b5f023162b..bb1fc4818e1 100644
> --- a/gcc/config/arm/neon.md
> +++ b/gcc/config/arm/neon.md
> @@ -981,7 +981,7 @@
>
> ;; Widening operations
>
> -(define_expand "widen_ssum<v_double_width><mode>3"
> +(define_expand "reduc_widen_ssum<v_double_width><mode>3"
> [(set (match_operand:<V_double_width> 0 "s_register_operand")
> (plus:<V_double_width>
> (sign_extend:<V_double_width>
> @@ -1040,7 +1040,7 @@
> }
> [(set_attr "type" "neon_add_widen")])
>
> -(define_insn "widen_ssum<V_widen_l><mode>3"
> +(define_insn "reduc_widen_ssum<V_widen_l><mode>3"
> [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
> (plus:<V_widen>
> (sign_extend:<V_widen>
> @@ -1051,7 +1051,7 @@
> [(set_attr "type" "neon_add_widen")]
> )
>
> -(define_expand "widen_usum<v_double_width><mode>3"
> +(define_expand "reduc_widen_usum<v_double_width><mode>3"
> [(set (match_operand:<V_double_width> 0 "s_register_operand")
> (plus:<V_double_width>
> (zero_extend:<V_double_width>
> @@ -1110,7 +1110,7 @@
> }
> [(set_attr "type" "neon_add_widen")])
>
> -(define_insn "widen_usum<V_widen_l><mode>3"
> +(define_insn "reduc_widen_usum<V_widen_l><mode>3"
> [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
> (plus:<V_widen> (zero_extend:<V_widen>
> (match_operand:VW 1 "s_register_operand" "%w"))
> diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
> index 1fa8ff2b00c..fce3fcc38c9 100644
> --- a/gcc/config/ia64/vect.md
> +++ b/gcc/config/ia64/vect.md
> @@ -584,7 +584,7 @@
> operands[1] = gen_lowpart (DImode, operands[1]);
> })
>
> -(define_expand "widen_usumv4hiv8qi3"
> +(define_expand "reduc_widen_usumv4hiv8qi3"
> [(match_operand:V4HI 0 "gr_register_operand" "")
> (match_operand:V8QI 1 "gr_register_operand" "")
> (match_operand:V4HI 2 "gr_register_operand" "")]
> @@ -594,7 +594,7 @@
> DONE;
> })
>
> -(define_expand "widen_usumv2siv4hi3"
> +(define_expand "reduc_widen_usumv2siv4hi3"
> [(match_operand:V2SI 0 "gr_register_operand" "")
> (match_operand:V4HI 1 "gr_register_operand" "")
> (match_operand:V2SI 2 "gr_register_operand" "")]
> @@ -604,7 +604,7 @@
> DONE;
> })
>
> -(define_expand "widen_ssumv4hiv8qi3"
> +(define_expand "reduc_widen_ssumv4hiv8qi3"
> [(match_operand:V4HI 0 "gr_register_operand" "")
> (match_operand:V8QI 1 "gr_register_operand" "")
> (match_operand:V4HI 2 "gr_register_operand" "")]
> @@ -614,7 +614,7 @@
> DONE;
> })
>
> -(define_expand "widen_ssumv2siv4hi3"
> +(define_expand "reduc_widen_ssumv2siv4hi3"
> [(match_operand:V2SI 0 "gr_register_operand" "")
> (match_operand:V4HI 1 "gr_register_operand" "")
> (match_operand:V2SI 2 "gr_register_operand" "")]
> diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
> index a8f8d039ffc..7e185f59c84 100644
> --- a/gcc/config/rs6000/altivec.md
> +++ b/gcc/config/rs6000/altivec.md
> @@ -3805,7 +3805,7 @@
> DONE;
> })
>
> -(define_expand "widen_usumv4si<mode>3"
> +(define_expand "reduc_widen_usumv4si<mode>3"
> [(set (match_operand:V4SI 0 "register_operand" "=v")
> (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
> (unspec:V4SI [(match_operand:VIshort 1 "register_operand"
> "v")]
> @@ -3819,7 +3819,7 @@
> DONE;
> })
>
> -(define_expand "widen_ssumv4siv16qi3"
> +(define_expand "reduc_widen_ssumv4siv16qi3"
> [(set (match_operand:V4SI 0 "register_operand" "=v")
> (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
> (unspec:V4SI [(match_operand:V16QI 1 "register_operand"
> "v")]
> @@ -3833,7 +3833,7 @@
> DONE;
> })
>
> -(define_expand "widen_ssumv4siv8hi3"
> +(define_expand "reduc_widen_ssumv4siv8hi3"
> [(set (match_operand:V4SI 0 "register_operand" "=v")
> (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
> (unspec:V4SI [(match_operand:V8HI 1 "register_operand"
> "v")]
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index c0026c17318..4b3dc950aeb 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -5091,10 +5091,10 @@ equal or wider than the mode of the absolute
> difference. The result is placed
> in operand 0, which is of the same mode as operand 3.
> @var{m} is the mode of operand 1 and operand 2.
>
> -@mdindex widen_ssum@var{n}@var{m}3
> -@mdindex widen_usum@var{n}@var{m}3
> -@item @samp{widen_ssum@var{n}@var{m}3}
> -@itemx @samp{widen_usum@var{n}@var{m}3}
> +@mdindex reduc_widen_ssum@var{n}@var{m}3
> +@mdindex reduc_widen_usum@var{n}@var{m}3
> +@item @samp{reduc_widen_ssum@var{n}@var{m}3}
> +@itemx @samp{reduc_widen_usum@var{n}@var{m}3}
> Operands 0 and 2 are of the same mode, which is wider than the mode of
> operand 1. Add operand 1 to operand 2 and place the widened result in
> operand 0. (This is used express accumulation of elements into an accumulator
> diff --git a/gcc/optabs-tree.cc b/gcc/optabs-tree.cc
> index 1b80cac85c7..b7a1cf1f7d8 100644
> --- a/gcc/optabs-tree.cc
> +++ b/gcc/optabs-tree.cc
> @@ -149,7 +149,8 @@ optab_for_tree_code (enum tree_code code, const_tree type,
> return vec_realign_load_optab;
>
> case WIDEN_SUM_EXPR:
> - return TYPE_UNSIGNED (type) ? usum_widen_optab : ssum_widen_optab;
> + return (TYPE_UNSIGNED (type)
> + ? reduc_widen_usum_optab : reduc_widen_ssum_optab);
>
> case DOT_PROD_EXPR:
> {
> diff --git a/gcc/optabs.def b/gcc/optabs.def
> index 7ccea18543f..327e3efaf8a 100644
> --- a/gcc/optabs.def
> +++ b/gcc/optabs.def
> @@ -85,8 +85,8 @@ OPTAB_CD(smsub_widen_optab, "msub$b$a4")
> OPTAB_CD(umsub_widen_optab, "umsub$b$a4")
> OPTAB_CD(ssmsub_widen_optab, "ssmsub$b$a4")
> OPTAB_CD(usmsub_widen_optab, "usmsub$a$b4")
> -OPTAB_CD(ssum_widen_optab, "widen_ssum$a$b3")
> -OPTAB_CD(usum_widen_optab, "widen_usum$a$b3")
> +OPTAB_CD(reduc_widen_ssum_optab, "reduc_widen_ssum$a$b3")
> +OPTAB_CD(reduc_widen_usum_optab, "reduc_widen_usum$a$b3")
> OPTAB_CD(crc_optab, "crc$a$b4")
> OPTAB_CD(crc_rev_optab, "crc_rev$a$b4")
> OPTAB_CD(vec_load_lanes_optab, "vec_load_lanes$a$b")
>
--
Richard Biener <[email protected]>
SUSE Software Solutions Germany GmbH,
Frankenstrasse 146, 90461 Nuernberg, Germany;
GF: Jochen Jaser, Andrew McDonald, Abhinav Puri; (HRB 36809, AG Nuernberg)
