hwprobe only arrived in Linux 6.4, so on an older kernel the syscall fails
and -march=native has nothing to say. /proc/cpuinfo has carried an ISA
string for far longer, so read that instead when the syscall is unavailable.
GCC_CPUINFO names a file to read instead of /proc/cpuinfo, and
GCC_CPUINFO_CPU the processor to look for in it, as on aarch64. Both
exist so that the parser can be tested on a machine unlike the one the
file describes.
The test input other than info_1 are /proc/cpuinfo output collected from
real machines:
info_0 SpacemiT X100 and A100, one block of each, from a machine
whose cores are not all alike
info_2 SiFive U74-MC, from a StarFive VisionFive 2
info_3 SpacemiT X60, from a Banana Pi BPI-F3
info_4 SiFive P870-D
info_1 is made up, naming extensions no compiler knows, so that
dropping them can be tested.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (standard_extensions_p):
Rename to...
(riscv_ext_is_known_p): ...this, and export.
(riscv_subset_list::parse_single_std_ext): Update the callers.
(riscv_subset_list::parse_single_multiletter_ext): Likewise.
* config/riscv/riscv-subset.h (riscv_ext_is_known_p): Declare.
* config/riscv/driver-riscv.cc: Include riscv-subset.h.
(riscv_native_arch): Split the hwprobe half out into...
(riscv_arch_from_hwprobe): ...this new function.
(struct riscv_cpuinfo): New.
(riscv_cpuinfo_file, riscv_cpuinfo_forced, riscv_cpuinfo_cpu)
(riscv_cpuinfo_field, riscv_read_cpuinfo, riscv_cpuinfo)
(riscv_filter_isa, riscv_arch_from_cpuinfo): New functions.
* config/riscv/x-riscv: Update the dependencies.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cpunative/riscv-cpunative.exp: New file.
* gcc.target/riscv/cpunative/info_0: New file.
* gcc.target/riscv/cpunative/info_1: New file.
* gcc.target/riscv/cpunative/info_2: New file.
* gcc.target/riscv/cpunative/info_3: New file.
* gcc.target/riscv/cpunative/info_4: New file.
* gcc.target/riscv/cpunative/native_cpu_0.c: New test.
* gcc.target/riscv/cpunative/native_cpu_1.c: New test.
* gcc.target/riscv/cpunative/native_cpu_2.c: New test.
* gcc.target/riscv/cpunative/native_cpu_3.c: New test.
* gcc.target/riscv/cpunative/native_cpu_4.c: New test.
* gcc.target/riscv/cpunative/native_cpu_5.c: New test.
* gcc.target/riscv/cpunative/native_cpu_6.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 15 +-
gcc/common/config/riscv/riscv-hwprobe.h | 3 +
gcc/config/riscv/driver-riscv.cc | 220 +++++++++++++-
gcc/config/riscv/riscv-subset.h | 1 +
gcc/config/riscv/x-riscv | 1 +
.../gcc.target/riscv/cpunative/info_0 | 20 ++
.../gcc.target/riscv/cpunative/info_1 | 10 +
.../gcc.target/riscv/cpunative/info_2 | 39 +++
.../gcc.target/riscv/cpunative/info_3 | 71 +++++
.../gcc.target/riscv/cpunative/info_4 | 287 ++++++++++++++++++
.../gcc.target/riscv/cpunative/native_cpu_0.c | 17 ++
.../gcc.target/riscv/cpunative/native_cpu_1.c | 17 ++
.../gcc.target/riscv/cpunative/native_cpu_2.c | 14 +
.../gcc.target/riscv/cpunative/native_cpu_3.c | 18 ++
.../gcc.target/riscv/cpunative/native_cpu_4.c | 17 ++
.../gcc.target/riscv/cpunative/native_cpu_5.c | 16 +
.../gcc.target/riscv/cpunative/native_cpu_6.c | 22 ++
.../riscv/cpunative/riscv-cpunative.exp | 35 +++
18 files changed, 814 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/info_0
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/info_1
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/info_2
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/info_3
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/info_4
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_0.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cpunative/riscv-cpunative.exp
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6bbbacab8df..0252a600287 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -522,10 +522,11 @@ subset_cmp (const std::string &a, const std::string &b)
}
}
-/* Return true if EXT is a standard extension. */
+/* Return true if EXT names an extension this compiler knows about, whether
+ standard or vendor defined. */
-static bool
-standard_extensions_p (const char *ext)
+bool
+riscv_ext_is_known_p (const char *ext)
{
auto itr = riscv_ext_infos.find (ext);
return itr != riscv_ext_infos.end ();
@@ -562,7 +563,7 @@ riscv_subset_list::add (const char *subset, int
major_version,
}
return;
}
- else if (strlen (subset) == 1 && !standard_extensions_p (subset))
+ else if (strlen (subset) == 1 && !riscv_ext_is_known_p (subset))
{
if (m_loc)
error_at (*m_loc,
@@ -571,7 +572,7 @@ riscv_subset_list::add (const char *subset, int
major_version,
m_arch, subset);
return;
}
- else if (subset[0] == 'z' && !standard_extensions_p (subset))
+ else if (subset[0] == 'z' && !riscv_ext_is_known_p (subset))
{
if (m_loc)
error_at (*m_loc,
@@ -580,7 +581,7 @@ riscv_subset_list::add (const char *subset, int
major_version,
m_arch, subset);
return;
}
- else if (subset[0] == 's' && !standard_extensions_p (subset))
+ else if (subset[0] == 's' && !riscv_ext_is_known_p (subset))
{
if (m_loc)
error_at (*m_loc,
@@ -589,7 +590,7 @@ riscv_subset_list::add (const char *subset, int
major_version,
m_arch, subset);
return;
}
- else if (subset[0] == 'x' && !standard_extensions_p (subset))
+ else if (subset[0] == 'x' && !riscv_ext_is_known_p (subset))
{
if (m_loc)
error_at (*m_loc,
diff --git a/gcc/common/config/riscv/riscv-hwprobe.h
b/gcc/common/config/riscv/riscv-hwprobe.h
index ba989b99d2f..9b66364427c 100644
--- a/gcc/common/config/riscv/riscv-hwprobe.h
+++ b/gcc/common/config/riscv/riscv-hwprobe.h
@@ -29,6 +29,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If
not, see
#ifndef __NR_riscv_hwprobe
#define __NR_riscv_hwprobe 258
#endif
+#ifndef __NR_getcpu
+#define __NR_getcpu 168
+#endif
enum {
#define RISCV_HWPROBE_KEY(NAME, VALUE) RISCV_HWPROBE_KEY_##NAME = VALUE,
diff --git a/gcc/config/riscv/driver-riscv.cc b/gcc/config/riscv/driver-riscv.cc
index 2997c5c2fe9..535ee49267c 100644
--- a/gcc/config/riscv/driver-riscv.cc
+++ b/gcc/config/riscv/driver-riscv.cc
@@ -24,6 +24,7 @@ along with GCC; see the file COPYING3. If not see
#include "system.h"
#include "coretypes.h"
#include "tm.h"
+#include "riscv-subset.h"
#ifdef __linux__
#include "common/config/riscv/riscv-hwprobe.h"
@@ -44,6 +45,20 @@ static const struct riscv_hwprobe_ext riscv_hwprobe_exts[] =
{
#include "common/config/riscv/riscv-hwprobe.def"
};
+/* Return the number of the CPU this process is currently running on, or -1
+ if it cannot be determined. */
+
+static int
+riscv_current_cpu (void)
+{
+ unsigned int cpu = 0;
+
+ if (syscall_5_args (__NR_getcpu, (long) &cpu, 0, 0, 0, 0) != 0)
+ return -1;
+
+ return (int) cpu;
+}
+
/* Append the Zvl extension for this machine's vector register width,
which only the vlenb CSR reports. */
@@ -111,6 +126,205 @@ riscv_arch_from_hwprobe (std::string &isa, bool *vector_p)
return true;
}
+/* What the /proc/cpuinfo fallback managed to read out of one processor
+ block. */
+
+struct riscv_cpuinfo
+{
+ std::string isa;
+};
+
+/* GCC_CPUINFO names a file to read instead of /proc/cpuinfo, and
+ GCC_CPUINFO_CPU the processor to look for in it. Both are for
+ testing. */
+
+static const char *
+riscv_cpuinfo_file (void)
+{
+ const char *path = getenv ("GCC_CPUINFO");
+
+ return path != NULL ? path : "/proc/cpuinfo";
+}
+
+static bool
+riscv_cpuinfo_forced (void)
+{
+ return getenv ("GCC_CPUINFO") != NULL;
+}
+
+static int
+riscv_cpuinfo_cpu (void)
+{
+ const char *forced = getenv ("GCC_CPUINFO_CPU");
+
+ return forced != NULL ? atoi (forced) : riscv_current_cpu ();
+}
+
+/* Split LINE, which /proc/cpuinfo writes as "name\t: value", putting the
+ name in NAME and returning the value. Both are stripped of surrounding
+ whitespace. Return NULL if LINE is not of that shape. */
+
+static const char *
+riscv_cpuinfo_field (char *line, std::string &name)
+{
+ char *colon = strchr (line, ':');
+ char *end;
+
+ if (colon == NULL)
+ return NULL;
+
+ end = colon;
+ while (end > line && ISSPACE (end[-1]))
+ end--;
+ name.assign (line, end - line);
+
+ colon++;
+ while (ISSPACE (*colon))
+ colon++;
+
+ end = colon + strlen (colon);
+ while (end > colon && ISSPACE (end[-1]))
+ end--;
+ *end = '\0';
+
+ return colon;
+}
+
+/* Read the /proc/cpuinfo block describing processor WANT into OUT, or the
+ first block in the file if WANT is negative. The processor field holds
+ the number sched_getcpu would return, not the hart id. Return false if
+ there is no such block, or if it says nothing about the ISA. */
+
+static bool
+riscv_read_cpuinfo (int want, struct riscv_cpuinfo *out)
+{
+ FILE *f = fopen (riscv_cpuinfo_file (), "r");
+ char line[1024];
+ bool in_block = false;
+ bool hart_isa_p = false;
+
+ if (f == NULL)
+ return false;
+
+ out->isa.clear ();
+
+ while (fgets (line, sizeof (line), f) != NULL)
+ {
+ std::string name;
+ const char *value = riscv_cpuinfo_field (line, name);
+
+ if (value == NULL)
+ continue;
+
+ if (name == "processor")
+ {
+ if (in_block)
+ break;
+ in_block = want < 0 || atoi (value) == want;
+ continue;
+ }
+
+ if (!in_block)
+ continue;
+
+ /* "hart isa" describes this core alone and is the one to go by, but
+ the kernels this fallback exists for are older than that line and
+ offer only the machine-wide "isa". */
+ if (name == "hart isa")
+ {
+ out->isa = value;
+ hart_isa_p = true;
+ }
+ else if (name == "isa" && !hart_isa_p)
+ out->isa = value;
+ }
+
+ fclose (f);
+
+ return !out->isa.empty ();
+}
+
+/* Read the block for the current CPU, or the first one if it has none. */
+
+static bool
+riscv_cpuinfo (struct riscv_cpuinfo *out)
+{
+ return (riscv_read_cpuinfo (riscv_cpuinfo_cpu (), out)
+ || riscv_read_cpuinfo (-1, out));
+}
+
+/* Copy KERNEL_ISA into ISA, dropping every extension this compiler does
+ not know: one unrecognised name would make -march= fail outright. Set
+ *VECTOR_P if what is left has vectors. Return false if KERNEL_ISA is
+ not an ISA string at all. */
+
+static bool
+riscv_filter_isa (const char *kernel_isa, std::string &isa, bool *vector_p)
+{
+ const char *base = __riscv_xlen == 32 ? "rv32" : "rv64";
+ const char *p = kernel_isa;
+
+ if (strncmp (p, base, 4) != 0)
+ return false;
+ p += 4;
+
+ if (*p != 'i' && *p != 'e' && *p != 'g')
+ return false;
+
+ isa = base;
+ isa += *p++;
+
+ /* The single-letter extensions run together up to the first underscore. */
+ for (; *p != '\0' && *p != '_'; p++)
+ {
+ const char name[2] = { *p, '\0' };
+
+ if (!riscv_ext_is_known_p (name))
+ continue;
+
+ isa += '_';
+ isa += *p;
+ if (*p == 'v')
+ *vector_p = true;
+ }
+
+ /* The multi-letter ones are separated by underscores. */
+ while (*p == '_')
+ {
+ const char *end = ++p;
+
+ while (*end != '\0' && *end != '_')
+ end++;
+
+ std::string name (p, end - p);
+ p = end;
+
+ if (name.empty () || !riscv_ext_is_known_p (name.c_str ()))
+ continue;
+
+ isa += '_';
+ isa += name;
+ if (name.compare (0, 3, "zve") == 0)
+ *vector_p = true;
+ }
+
+ return true;
+}
+
+/* Build the ISA string from /proc/cpuinfo, for kernels that are too old to
+ have hwprobe. */
+
+static bool
+riscv_arch_from_cpuinfo (std::string &isa, bool *vector_p)
+{
+ struct riscv_cpuinfo info;
+
+ if (!riscv_cpuinfo (&info))
+ return false;
+
+ return riscv_filter_isa (info.isa.c_str (), isa, vector_p);
+}
+
/* Return the ISA string describing this machine, or NULL if it cannot be
determined. */
@@ -119,11 +333,13 @@ riscv_native_arch (void)
{
std::string isa;
bool vector_p = false;
+ bool forced = riscv_cpuinfo_forced ();
- if (!riscv_arch_from_hwprobe (isa, &vector_p))
+ if ((forced || !riscv_arch_from_hwprobe (isa, &vector_p))
+ && !riscv_arch_from_cpuinfo (isa, &vector_p))
return NULL;
- if (vector_p)
+ if (vector_p && !forced)
riscv_add_vlen (isa);
return xstrdup (isa.c_str ());
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index 2f7d943613f..19ccb0a4fdb 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -178,6 +178,7 @@ public:
const_iterator end() const { return const_iterator(nullptr); }
};
+extern bool riscv_ext_is_known_p (const char *);
extern const riscv_subset_list *riscv_cmdline_subset_list (void);
extern void
riscv_set_arch_by_subset_list (riscv_subset_list *, struct gcc_options *);
diff --git a/gcc/config/riscv/x-riscv b/gcc/config/riscv/x-riscv
index 55f32d7dd1c..d1c59ba50e0 100644
--- a/gcc/config/riscv/x-riscv
+++ b/gcc/config/riscv/x-riscv
@@ -1,5 +1,6 @@
driver-riscv.o: $(srcdir)/config/riscv/driver-riscv.cc \
$(CONFIG_H) $(SYSTEM_H) $(TM_H) $(CORETYPES_H) \
+ $(srcdir)/config/riscv/riscv-subset.h \
$(srcdir)/common/config/riscv/riscv-hwprobe.h \
$(srcdir)/common/config/riscv/riscv-hwprobe.def
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/info_0
b/gcc/testsuite/gcc.target/riscv/cpunative/info_0
new file mode 100644
index 00000000000..d86dc23aee5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/info_0
@@ -0,0 +1,20 @@
+processor : 0
+hart : 0
+model name : Spacemit(R) X100
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfh_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbc_zbs_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh_zvkt_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_sdtrig
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000002
+mimpid : 0x33d8a600
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfh_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbc_zbs_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh_zvkt_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_sdtrig
+
+processor : 8
+hart : 8
+model name : Spacemit(R) A100
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfh_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbc_zbs_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh_zvkt_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_sdtrig
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000041000002
+mimpid : 0x10000000d5686200
+hart isa :
rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfh_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbc_zbs_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh_zvkt_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_sdtrig
+
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/info_1
b/gcc/testsuite/gcc.target/riscv/cpunative/info_1
new file mode 100644
index 00000000000..6a3709c5456
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/info_1
@@ -0,0 +1,10 @@
+processor : 0
+hart : 0
+model name : Nonesuch
+isa : rv64imafdc_znosuchext_zba_xmadeup_zbb
+mmu : sv39
+mvendorid : 0xdead
+marchid : 0xbeef
+mimpid : 0x1
+hart isa : rv64imafdc_znosuchext_zba_xmadeup_zbb
+
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/info_2
b/gcc/testsuite/gcc.target/riscv/cpunative/info_2
new file mode 100644
index 00000000000..500ad48d420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/info_2
@@ -0,0 +1,39 @@
+processor : 0
+hart : 2
+isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+mmu : sv39
+uarch : sifive,u74-mc
+mvendorid : 0x489
+marchid : 0x8000000000000007
+mimpid : 0x4210427
+hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+
+processor : 1
+hart : 1
+isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+mmu : sv39
+uarch : sifive,u74-mc
+mvendorid : 0x489
+marchid : 0x8000000000000007
+mimpid : 0x4210427
+hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+
+processor : 2
+hart : 3
+isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+mmu : sv39
+uarch : sifive,u74-mc
+mvendorid : 0x489
+marchid : 0x8000000000000007
+mimpid : 0x4210427
+hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+
+processor : 3
+hart : 4
+isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
+mmu : sv39
+uarch : sifive,u74-mc
+mvendorid : 0x489
+marchid : 0x8000000000000007
+mimpid : 0x4210427
+hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/info_3
b/gcc/testsuite/gcc.target/riscv/cpunative/info_3
new file mode 100644
index 00000000000..ff24857b4a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/info_3
@@ -0,0 +1,71 @@
+processor : 0
+hart : 0
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 1
+hart : 1
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 2
+hart : 2
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 3
+hart : 3
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 4
+hart : 4
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 5
+hart : 5
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 6
+hart : 6
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
+
+processor : 7
+hart : 7
+model name : Spacemit(R) X60
+isa :
rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
+mmu : sv39
+mvendorid : 0x710
+marchid : 0x8000000058000001
+mimpid : 0x1000000049772200
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/info_4
b/gcc/testsuite/gcc.target/riscv/cpunative/info_4
new file mode 100644
index 00000000000..3082d576e6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/info_4
@@ -0,0 +1,287 @@
+processor : 0
+hart : 0
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 1
+hart : 1
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 2
+hart : 2
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 3
+hart : 3
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 4
+hart : 4
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 5
+hart : 5
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 6
+hart : 6
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 7
+hart : 7
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 8
+hart : 8
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 9
+hart : 9
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 10
+hart : 10
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 11
+hart : 11
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 12
+hart : 12
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 13
+hart : 13
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 14
+hart : 14
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 15
+hart : 15
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 16
+hart : 16
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 17
+hart : 17
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 18
+hart : 18
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 19
+hart : 19
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 20
+hart : 20
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 21
+hart : 21
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 22
+hart : 22
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 23
+hart : 23
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 24
+hart : 24
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 25
+hart : 25
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 26
+hart : 26
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 27
+hart : 27
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 28
+hart : 28
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 29
+hart : 29
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 30
+hart : 30
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+
+processor : 31
+hart : 31
+isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
+mmu : sv48
+mvendorid : 0x489
+marchid : 0x8000000000000109
+mimpid : 0x14250606
+hart isa :
rv64imafdcvh_zicbom_zicbop_zicboz_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zaamo_zalrsc_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvkb_zvkg_zvkned_zvknhb_zvksed_zvksh_zvkt_smaia_smmpm_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_0.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_0.c
new file mode 100644
index 00000000000..bdac433d381
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_0.c
@@ -0,0 +1,17 @@
+/* The X100 half of a heterogeneous machine. Its hart implements H, and
+ the compiler is told it is running on that core. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_0" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "0" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch, "rv64i2p1[^"]*_h1p0_} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_1.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_1.c
new file mode 100644
index 00000000000..a958e8c541a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_1.c
@@ -0,0 +1,17 @@
+/* Real /proc/cpuinfo from a spacemit K3. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_0" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "8" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch, "rv64i2p1[^"]*_v1p0_} } } */
+/* { dg-final { scan-assembler-not {\.attribute arch, "[^"]*_h1p0_} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_2.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_2.c
new file mode 100644
index 00000000000..adccb7ea7cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_0" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "99" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch, "rv64i2p1[^"]*_h1p0_} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_3.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_3.c
new file mode 100644
index 00000000000..8fbcb75b187
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_3.c
@@ -0,0 +1,18 @@
+/* Testcase with unknown ext in /proc/cpuinfo. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_1" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "0" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch,
"rv64i2p1[^"]*_zba1p0_zbb1p0} } } */
+/* { dg-final { scan-assembler-not {znosuchext} } } */
+/* { dg-final { scan-assembler-not {xmadeup} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_4.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_4.c
new file mode 100644
index 00000000000..58bb4aeef9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_4.c
@@ -0,0 +1,17 @@
+/* A real /proc/cpuinfo from StarFive VisionFive 2. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_2" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "2" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch,
"rv64i2p1[^"]*_zba1p0_zbb1p0"} } } */
+/* { dg-final { scan-assembler-not {\.attribute arch, "[^"]*_v1p0_} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_5.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_5.c
new file mode 100644
index 00000000000..656b44f011e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_5.c
@@ -0,0 +1,16 @@
+/* Real /proc/cpuinfo from a Banana Pi BPI-F3. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_3" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "0" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch,
"rv64i2p1[^"]*_v1p0_[^"]*_zvfh1p0_} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_6.c
b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_6.c
new file mode 100644
index 00000000000..823fcd79b54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/native_cpu_6.c
@@ -0,0 +1,22 @@
+/* A real /proc/cpuinfo, from a SiFive P870-D. It is the last of the
+ thirty-two blocks that are asked for here, and the ISA string is the
+ longest and the most recent of any file in this directory, carrying
+ names -- zfbfmin, zvfbfwma, smmpm, ssnpm, svade -- that the others
+ do not. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target riscv_native_cpu_detect } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-set-compiler-env-var GCC_CPUINFO
"$srcdir/gcc.target/riscv/cpunative/info_4" } */
+/* { dg-set-compiler-env-var GCC_CPUINFO_CPU "31" } */
+/* { dg-additional-options "-march=native -mabi=lp64d -fverbose-asm" } */
+
+int
+main (void)
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.attribute arch, "rv64i2p1[^"]*_zfbfmin1p0_}
} } */
+/* { dg-final { scan-assembler {\.attribute arch, "[^"]*_zvfbfwma1p0_} } } */
+/* { dg-final { scan-assembler {\.attribute arch, "[^"]*_svade1p0_} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpunative/riscv-cpunative.exp
b/gcc/testsuite/gcc.target/riscv/cpunative/riscv-cpunative.exp
new file mode 100644
index 00000000000..21353ea0593
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpunative/riscv-cpunative.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv*-*-*] then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+ "" ""
+
+# All done.
+dg-finish
--
2.53.0
