Extract the hwprobe key numbers and extension bits into
common/config/riscv/riscv-hwprobe.def, with the syscall wrapper in
riscv-hwprobe.h, so that the -march=native implementation can share the
description libgcc already needs.
gcc/ChangeLog:
* common/config/riscv/riscv-hwprobe.def: New file.
* common/config/riscv/riscv-hwprobe.h: New file.
libgcc/ChangeLog:
* config/riscv/feature_bits.c: Include
common/config/riscv/riscv-hwprobe.h, and drop the hwprobe key
numbers, extension bit positions, struct riscv_hwprobe and
syscall_5_args that moved there.
(__init_riscv_features_bits_linux): Set the extension bits from
riscv-hwprobe.def.
(__init_riscv_feature_bits): Add a declaration.
---
gcc/common/config/riscv/riscv-hwprobe.def | 146 ++++++++++++++++
gcc/common/config/riscv/riscv-hwprobe.h | 85 ++++++++++
libgcc/config/riscv/feature_bits.c | 194 +---------------------
3 files changed, 240 insertions(+), 185 deletions(-)
create mode 100644 gcc/common/config/riscv/riscv-hwprobe.def
create mode 100644 gcc/common/config/riscv/riscv-hwprobe.h
diff --git a/gcc/common/config/riscv/riscv-hwprobe.def
b/gcc/common/config/riscv/riscv-hwprobe.def
new file mode 100644
index 00000000000..92eda025401
--- /dev/null
+++ b/gcc/common/config/riscv/riscv-hwprobe.def
@@ -0,0 +1,146 @@
+/* Description of the Linux riscv_hwprobe interface.
+
+ Copyright (C) 2026 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+/* This transcribes the part of <asm/hwprobe.h> that both the compiler and
+ libgcc need. It is a stable Linux ABI, transcribed rather than included
+ so that neither the driver nor libgcc depends on the kernel headers being
+ installed, or on a glibc new enough to provide <sys/hwprobe.h>.
+
+ The file is written to be read more than once. Before each #include,
+ define whichever of these macros you want:
+
+ RISCV_HWPROBE_KEY (NAME, VALUE)
+
+ NAME is the key name without its RISCV_HWPROBE_KEY_ prefix, and VALUE
+ is the number the kernel knows it by.
+
+ RISCV_HWPROBE_EXT (NAME, UPPERCASE_NAME, KEY, BIT, XLEN)
+
+ NAME is the extension name as it appears in an ISA string,
+ UPPERCASE_NAME is the same name as an upper case token, KEY names the
+ key whose value holds the bit, BIT is the bit position within that
+ value, and XLEN is 32 or 64 if the extension only exists on that XLEN,
+ or 0 if it exists on both.
+
+ RISCV_HWPROBE_IMA_FD covers both F and D, so bit 0 of IMA_EXT_0 has two
+ entries. Extensions implied by others are listed all the same; callers
+ that care must drop the redundant ones themselves. */
+
+#ifndef RISCV_HWPROBE_KEY
+#define RISCV_HWPROBE_KEY(NAME, VALUE)
+#endif
+
+#ifndef RISCV_HWPROBE_EXT
+#define RISCV_HWPROBE_EXT(NAME, UPPERCASE_NAME, KEY, BIT, XLEN)
+#endif
+
+RISCV_HWPROBE_KEY (MVENDORID, 0)
+RISCV_HWPROBE_KEY (MARCHID, 1)
+RISCV_HWPROBE_KEY (MIMPID, 2)
+RISCV_HWPROBE_KEY (BASE_BEHAVIOR, 3)
+RISCV_HWPROBE_KEY (IMA_EXT_0, 4)
+RISCV_HWPROBE_KEY (CPUPERF_0, 5)
+RISCV_HWPROBE_KEY (ZICBOZ_BLOCK_SIZE, 6)
+RISCV_HWPROBE_KEY (HIGHEST_VIRT_ADDRESS, 7)
+RISCV_HWPROBE_KEY (TIME_CSR_FREQ, 8)
+RISCV_HWPROBE_KEY (MISALIGNED_SCALAR_PERF, 9)
+RISCV_HWPROBE_KEY (MISALIGNED_VECTOR_PERF, 10)
+RISCV_HWPROBE_KEY (VENDOR_EXT_THEAD_0, 11)
+RISCV_HWPROBE_KEY (ZICBOM_BLOCK_SIZE, 12)
+RISCV_HWPROBE_KEY (VENDOR_EXT_SIFIVE_0, 13)
+RISCV_HWPROBE_KEY (VENDOR_EXT_MIPS_0, 14)
+RISCV_HWPROBE_KEY (IMA_EXT_1, 16)
+
+RISCV_HWPROBE_EXT ("f", F, RISCV_HWPROBE_KEY_IMA_EXT_0, 0, 0)
+RISCV_HWPROBE_EXT ("d", D, RISCV_HWPROBE_KEY_IMA_EXT_0, 0, 0)
+RISCV_HWPROBE_EXT ("c", C, RISCV_HWPROBE_KEY_IMA_EXT_0, 1, 0)
+RISCV_HWPROBE_EXT ("v", V, RISCV_HWPROBE_KEY_IMA_EXT_0, 2, 0)
+RISCV_HWPROBE_EXT ("zba", ZBA, RISCV_HWPROBE_KEY_IMA_EXT_0, 3, 0)
+RISCV_HWPROBE_EXT ("zbb", ZBB, RISCV_HWPROBE_KEY_IMA_EXT_0, 4, 0)
+RISCV_HWPROBE_EXT ("zbs", ZBS, RISCV_HWPROBE_KEY_IMA_EXT_0, 5, 0)
+RISCV_HWPROBE_EXT ("zicboz", ZICBOZ, RISCV_HWPROBE_KEY_IMA_EXT_0, 6, 0)
+RISCV_HWPROBE_EXT ("zbc", ZBC, RISCV_HWPROBE_KEY_IMA_EXT_0, 7, 0)
+RISCV_HWPROBE_EXT ("zbkb", ZBKB, RISCV_HWPROBE_KEY_IMA_EXT_0, 8, 0)
+RISCV_HWPROBE_EXT ("zbkc", ZBKC, RISCV_HWPROBE_KEY_IMA_EXT_0, 9, 0)
+RISCV_HWPROBE_EXT ("zbkx", ZBKX, RISCV_HWPROBE_KEY_IMA_EXT_0, 10, 0)
+RISCV_HWPROBE_EXT ("zknd", ZKND, RISCV_HWPROBE_KEY_IMA_EXT_0, 11, 0)
+RISCV_HWPROBE_EXT ("zkne", ZKNE, RISCV_HWPROBE_KEY_IMA_EXT_0, 12, 0)
+RISCV_HWPROBE_EXT ("zknh", ZKNH, RISCV_HWPROBE_KEY_IMA_EXT_0, 13, 0)
+RISCV_HWPROBE_EXT ("zksed", ZKSED, RISCV_HWPROBE_KEY_IMA_EXT_0, 14, 0)
+RISCV_HWPROBE_EXT ("zksh", ZKSH, RISCV_HWPROBE_KEY_IMA_EXT_0, 15, 0)
+RISCV_HWPROBE_EXT ("zkt", ZKT, RISCV_HWPROBE_KEY_IMA_EXT_0, 16, 0)
+RISCV_HWPROBE_EXT ("zvbb", ZVBB, RISCV_HWPROBE_KEY_IMA_EXT_0, 17, 0)
+RISCV_HWPROBE_EXT ("zvbc", ZVBC, RISCV_HWPROBE_KEY_IMA_EXT_0, 18, 0)
+RISCV_HWPROBE_EXT ("zvkb", ZVKB, RISCV_HWPROBE_KEY_IMA_EXT_0, 19, 0)
+RISCV_HWPROBE_EXT ("zvkg", ZVKG, RISCV_HWPROBE_KEY_IMA_EXT_0, 20, 0)
+RISCV_HWPROBE_EXT ("zvkned", ZVKNED, RISCV_HWPROBE_KEY_IMA_EXT_0, 21, 0)
+RISCV_HWPROBE_EXT ("zvknha", ZVKNHA, RISCV_HWPROBE_KEY_IMA_EXT_0, 22, 0)
+RISCV_HWPROBE_EXT ("zvknhb", ZVKNHB, RISCV_HWPROBE_KEY_IMA_EXT_0, 23, 0)
+RISCV_HWPROBE_EXT ("zvksed", ZVKSED, RISCV_HWPROBE_KEY_IMA_EXT_0, 24, 0)
+RISCV_HWPROBE_EXT ("zvksh", ZVKSH, RISCV_HWPROBE_KEY_IMA_EXT_0, 25, 0)
+RISCV_HWPROBE_EXT ("zvkt", ZVKT, RISCV_HWPROBE_KEY_IMA_EXT_0, 26, 0)
+RISCV_HWPROBE_EXT ("zfh", ZFH, RISCV_HWPROBE_KEY_IMA_EXT_0, 27, 0)
+RISCV_HWPROBE_EXT ("zfhmin", ZFHMIN, RISCV_HWPROBE_KEY_IMA_EXT_0, 28, 0)
+RISCV_HWPROBE_EXT ("zihintntl", ZIHINTNTL, RISCV_HWPROBE_KEY_IMA_EXT_0, 29, 0)
+RISCV_HWPROBE_EXT ("zvfh", ZVFH, RISCV_HWPROBE_KEY_IMA_EXT_0, 30, 0)
+RISCV_HWPROBE_EXT ("zvfhmin", ZVFHMIN, RISCV_HWPROBE_KEY_IMA_EXT_0, 31, 0)
+RISCV_HWPROBE_EXT ("zfa", ZFA, RISCV_HWPROBE_KEY_IMA_EXT_0, 32, 0)
+RISCV_HWPROBE_EXT ("ztso", ZTSO, RISCV_HWPROBE_KEY_IMA_EXT_0, 33, 0)
+RISCV_HWPROBE_EXT ("zacas", ZACAS, RISCV_HWPROBE_KEY_IMA_EXT_0, 34, 0)
+RISCV_HWPROBE_EXT ("zicond", ZICOND, RISCV_HWPROBE_KEY_IMA_EXT_0, 35, 0)
+RISCV_HWPROBE_EXT ("zihintpause", ZIHINTPAUSE,
+ RISCV_HWPROBE_KEY_IMA_EXT_0, 36, 0)
+RISCV_HWPROBE_EXT ("zve32x", ZVE32X, RISCV_HWPROBE_KEY_IMA_EXT_0, 37, 0)
+RISCV_HWPROBE_EXT ("zve32f", ZVE32F, RISCV_HWPROBE_KEY_IMA_EXT_0, 38, 0)
+RISCV_HWPROBE_EXT ("zve64x", ZVE64X, RISCV_HWPROBE_KEY_IMA_EXT_0, 39, 0)
+RISCV_HWPROBE_EXT ("zve64f", ZVE64F, RISCV_HWPROBE_KEY_IMA_EXT_0, 40, 0)
+RISCV_HWPROBE_EXT ("zve64d", ZVE64D, RISCV_HWPROBE_KEY_IMA_EXT_0, 41, 0)
+RISCV_HWPROBE_EXT ("zimop", ZIMOP, RISCV_HWPROBE_KEY_IMA_EXT_0, 42, 0)
+RISCV_HWPROBE_EXT ("zca", ZCA, RISCV_HWPROBE_KEY_IMA_EXT_0, 43, 0)
+RISCV_HWPROBE_EXT ("zcb", ZCB, RISCV_HWPROBE_KEY_IMA_EXT_0, 44, 0)
+RISCV_HWPROBE_EXT ("zcd", ZCD, RISCV_HWPROBE_KEY_IMA_EXT_0, 45, 0)
+RISCV_HWPROBE_EXT ("zcf", ZCF, RISCV_HWPROBE_KEY_IMA_EXT_0, 46, 32)
+RISCV_HWPROBE_EXT ("zcmop", ZCMOP, RISCV_HWPROBE_KEY_IMA_EXT_0, 47, 0)
+RISCV_HWPROBE_EXT ("zawrs", ZAWRS, RISCV_HWPROBE_KEY_IMA_EXT_0, 48, 0)
+RISCV_HWPROBE_EXT ("supm", SUPM, RISCV_HWPROBE_KEY_IMA_EXT_0, 49, 0)
+RISCV_HWPROBE_EXT ("zicntr", ZICNTR, RISCV_HWPROBE_KEY_IMA_EXT_0, 50, 0)
+RISCV_HWPROBE_EXT ("zihpm", ZIHPM, RISCV_HWPROBE_KEY_IMA_EXT_0, 51, 0)
+RISCV_HWPROBE_EXT ("zfbfmin", ZFBFMIN, RISCV_HWPROBE_KEY_IMA_EXT_0, 52, 0)
+RISCV_HWPROBE_EXT ("zvfbfmin", ZVFBFMIN, RISCV_HWPROBE_KEY_IMA_EXT_0, 53, 0)
+RISCV_HWPROBE_EXT ("zvfbfwma", ZVFBFWMA, RISCV_HWPROBE_KEY_IMA_EXT_0, 54, 0)
+RISCV_HWPROBE_EXT ("zicbom", ZICBOM, RISCV_HWPROBE_KEY_IMA_EXT_0, 55, 0)
+RISCV_HWPROBE_EXT ("zaamo", ZAAMO, RISCV_HWPROBE_KEY_IMA_EXT_0, 56, 0)
+RISCV_HWPROBE_EXT ("zalrsc", ZALRSC, RISCV_HWPROBE_KEY_IMA_EXT_0, 57, 0)
+RISCV_HWPROBE_EXT ("zabha", ZABHA, RISCV_HWPROBE_KEY_IMA_EXT_0, 58, 0)
+RISCV_HWPROBE_EXT ("zalasr", ZALASR, RISCV_HWPROBE_KEY_IMA_EXT_0, 59, 0)
+RISCV_HWPROBE_EXT ("zicbop", ZICBOP, RISCV_HWPROBE_KEY_IMA_EXT_0, 60, 0)
+RISCV_HWPROBE_EXT ("zilsd", ZILSD, RISCV_HWPROBE_KEY_IMA_EXT_0, 61, 32)
+RISCV_HWPROBE_EXT ("zclsd", ZCLSD, RISCV_HWPROBE_KEY_IMA_EXT_0, 62, 32)
+RISCV_HWPROBE_EXT ("zicfilp", ZICFILP, RISCV_HWPROBE_KEY_IMA_EXT_0, 63, 0)
+
+RISCV_HWPROBE_EXT ("zicfiss", ZICFISS, RISCV_HWPROBE_KEY_IMA_EXT_1, 0, 0)
+
+#undef RISCV_HWPROBE_KEY
+#undef RISCV_HWPROBE_EXT
diff --git a/gcc/common/config/riscv/riscv-hwprobe.h
b/gcc/common/config/riscv/riscv-hwprobe.h
new file mode 100644
index 00000000000..f1fe2aeac2c
--- /dev/null
+++ b/gcc/common/config/riscv/riscv-hwprobe.h
@@ -0,0 +1,85 @@
+/* Definitions for the Linux riscv_hwprobe interface.
+
+ Copyright (C) 2026 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_RISCV_HWPROBE_H
+#define GCC_RISCV_HWPROBE_H
+
+#ifndef __NR_riscv_hwprobe
+#define __NR_riscv_hwprobe 258
+#endif
+
+enum {
+#define RISCV_HWPROBE_KEY(NAME, VALUE) RISCV_HWPROBE_KEY_##NAME = VALUE,
+#include "common/config/riscv/riscv-hwprobe.def"
+};
+
+#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1ULL << 0)
+#define RISCV_HWPROBE_IMA_FD (1ULL << 0)
+#define RISCV_HWPROBE_IMA_C (1ULL << 1)
+#define RISCV_HWPROBE_IMA_V (1ULL << 2)
+
+struct riscv_hwprobe {
+ long long key;
+ unsigned long long value;
+};
+
+static inline long
+syscall_5_args (long number, long arg1, long arg2, long arg3,
+ long arg4, long arg5)
+{
+ register long a7 __asm__ ("a7") = number;
+ register long a0 __asm__ ("a0") = arg1;
+ register long a1 __asm__ ("a1") = arg2;
+ register long a2 __asm__ ("a2") = arg3;
+ register long a3 __asm__ ("a3") = arg4;
+ register long a4 __asm__ ("a4") = arg5;
+ __asm__ __volatile__ ("ecall\n\t"
+ : "=r"(a0)
+ : "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
+ : "memory");
+ return a0;
+}
+
+static inline long
+riscv_hwprobe (struct riscv_hwprobe *hwprobes, long npairs)
+{
+ return syscall_5_args (__NR_riscv_hwprobe, (long)hwprobes, npairs, 0,
+ 0, 0);
+}
+
+static inline unsigned long long
+riscv_hwprobe_value (const struct riscv_hwprobe *pairs, int npairs,
+ long long key)
+{
+ int i;
+
+ for (i = 0; i < npairs; i++)
+ if (pairs[i].key == key)
+ return pairs[i].value;
+
+ return 0;
+}
+
+#endif
diff --git a/libgcc/config/riscv/feature_bits.c
b/libgcc/config/riscv/feature_bits.c
index 8d226502eb7..af07fd6b30c 100644
--- a/libgcc/config/riscv/feature_bits.c
+++ b/libgcc/config/riscv/feature_bits.c
@@ -190,119 +190,7 @@ struct {
#define SET_EXT(EXT) features[EXT##_GROUPID] |= EXT##_BITMASK
#ifdef __linux
-
-#define __NR_riscv_hwprobe 258
-#define RISCV_HWPROBE_KEY_MVENDORID 0
-#define RISCV_HWPROBE_KEY_MARCHID 1
-#define RISCV_HWPROBE_KEY_MIMPID 2
-#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
-#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1ULL << 0)
-#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
-#define RISCV_HWPROBE_IMA_FD (1ULL << 0)
-#define RISCV_HWPROBE_IMA_C (1ULL << 1)
-#define RISCV_HWPROBE_IMA_V (1ULL << 2)
-#define RISCV_HWPROBE_EXT_ZBA (1ULL << 3)
-#define RISCV_HWPROBE_EXT_ZBB (1ULL << 4)
-#define RISCV_HWPROBE_EXT_ZBS (1ULL << 5)
-#define RISCV_HWPROBE_EXT_ZICBOZ (1ULL << 6)
-#define RISCV_HWPROBE_EXT_ZBC (1ULL << 7)
-#define RISCV_HWPROBE_EXT_ZBKB (1ULL << 8)
-#define RISCV_HWPROBE_EXT_ZBKC (1ULL << 9)
-#define RISCV_HWPROBE_EXT_ZBKX (1ULL << 10)
-#define RISCV_HWPROBE_EXT_ZKND (1ULL << 11)
-#define RISCV_HWPROBE_EXT_ZKNE (1ULL << 12)
-#define RISCV_HWPROBE_EXT_ZKNH (1ULL << 13)
-#define RISCV_HWPROBE_EXT_ZKSED (1ULL << 14)
-#define RISCV_HWPROBE_EXT_ZKSH (1ULL << 15)
-#define RISCV_HWPROBE_EXT_ZKT (1ULL << 16)
-#define RISCV_HWPROBE_EXT_ZVBB (1ULL << 17)
-#define RISCV_HWPROBE_EXT_ZVBC (1ULL << 18)
-#define RISCV_HWPROBE_EXT_ZVKB (1ULL << 19)
-#define RISCV_HWPROBE_EXT_ZVKG (1ULL << 20)
-#define RISCV_HWPROBE_EXT_ZVKNED (1ULL << 21)
-#define RISCV_HWPROBE_EXT_ZVKNHA (1ULL << 22)
-#define RISCV_HWPROBE_EXT_ZVKNHB (1ULL << 23)
-#define RISCV_HWPROBE_EXT_ZVKSED (1ULL << 24)
-#define RISCV_HWPROBE_EXT_ZVKSH (1ULL << 25)
-#define RISCV_HWPROBE_EXT_ZVKT (1ULL << 26)
-#define RISCV_HWPROBE_EXT_ZFH (1ULL << 27)
-#define RISCV_HWPROBE_EXT_ZFHMIN (1ULL << 28)
-#define RISCV_HWPROBE_EXT_ZIHINTNTL (1ULL << 29)
-#define RISCV_HWPROBE_EXT_ZVFH (1ULL << 30)
-#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
-#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
-#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
-#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
-#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
-#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
-#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 37)
-#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 38)
-#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39)
-#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40)
-#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41)
-#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 42)
-#define RISCV_HWPROBE_EXT_ZCA (1ULL << 43)
-#define RISCV_HWPROBE_EXT_ZCB (1ULL << 44)
-#define RISCV_HWPROBE_EXT_ZCD (1ULL << 45)
-#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
-#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
-#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
-#define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
-#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 50)
-#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 51)
-#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 52)
-#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53)
-#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54)
-#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
-#define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
-#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
-#define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
-#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
-#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 60)
-#define RISCV_HWPROBE_EXT_ZILSD (1ULL << 61)
-#define RISCV_HWPROBE_EXT_ZCLSD (1ULL << 62)
-#define RISCV_HWPROBE_EXT_ZICFILP (1ULL << 63)
-#define RISCV_HWPROBE_KEY_CPUPERF_0 5
-#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
-#define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
-#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
-#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
-#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
-#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
-#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
-#define RISCV_HWPROBE_KEY_IMA_EXT_1 16
-#define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0)
-
-struct riscv_hwprobe {
- long long key;
- unsigned long long value;
-};
-
-static long syscall_5_args (long number, long arg1, long arg2, long arg3,
- long arg4, long arg5)
-{
- register long a7 __asm__ ("a7") = number;
- register long a0 __asm__ ("a0") = arg1;
- register long a1 __asm__ ("a1") = arg2;
- register long a2 __asm__ ("a2") = arg3;
- register long a3 __asm__ ("a3") = arg4;
- register long a4 __asm__ ("a4") = arg5;
- __asm__ __volatile__ ("ecall\n\t"
- : "=r"(a0)
- : "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
- : "memory");
- return a0;
-}
-
-#define SET_FROM_HWPROBE(HWPROBE_VAR, EXT) \
- if (HWPROBE_VAR.value & RISCV_HWPROBE_EXT_##EXT) \
- SET_EXT (EXT)
-
-#define SET_FROM_IMA_EXT(EXT) \
- SET_FROM_HWPROBE (hwprobe_ima_ext, EXT)
-
-#define SET_FROM_IMA_EXT_1(EXT) \
- SET_FROM_HWPROBE (hwprobe_ima_ext_1, EXT)
+#include "common/config/riscv/riscv-hwprobe.h"
static void __init_riscv_features_bits_linux ()
{
@@ -314,10 +202,9 @@ static void __init_riscv_features_bits_linux ()
{RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
{RISCV_HWPROBE_KEY_IMA_EXT_1, 0},
};
+ const int npairs = sizeof (hwprobes) / sizeof (hwprobes[0]);
- long res = syscall_5_args (__NR_riscv_hwprobe, (long)&hwprobes,
- sizeof (hwprobes) / sizeof (hwprobes[0]), 0,
- 0, 0);
+ long res = riscv_hwprobe (hwprobes, npairs);
if (res)
return;
@@ -354,7 +241,6 @@ static void __init_riscv_features_bits_linux ()
1. The new extension implies a previous extension (e.g., Zve32f -> F).
2. The extensions imply some other extensions appear in the same release
version of Linux Kernel (e.g., Zbc - > Zbkc). */
-
if (hwprobe_ima_ext.value & RISCV_HWPROBE_IMA_FD)
{
SET_EXT (F);
@@ -385,74 +271,10 @@ static void __init_riscv_features_bits_linux ()
SET_EXT (ZVE64D);
}
- SET_FROM_IMA_EXT (ZBA);
- SET_FROM_IMA_EXT (ZBB);
- SET_FROM_IMA_EXT (ZBS);
- /* Added since Linux v6.7. */
- SET_FROM_IMA_EXT (ZICBOZ);
- /* Added since Linux v6.8. */
- SET_FROM_IMA_EXT (ZBC);
- SET_FROM_IMA_EXT (ZBKB);
- SET_FROM_IMA_EXT (ZBKC);
- SET_FROM_IMA_EXT (ZBKX);
- SET_FROM_IMA_EXT (ZKND);
- SET_FROM_IMA_EXT (ZKNE);
- SET_FROM_IMA_EXT (ZKNH);
- SET_FROM_IMA_EXT (ZKSED);
- SET_FROM_IMA_EXT (ZKSH);
- SET_FROM_IMA_EXT (ZKT);
- SET_FROM_IMA_EXT (ZVBB);
- SET_FROM_IMA_EXT (ZVBC);
- SET_FROM_IMA_EXT (ZVKB);
- SET_FROM_IMA_EXT (ZVKG);
- SET_FROM_IMA_EXT (ZVKNED);
- SET_FROM_IMA_EXT (ZVKNHA);
- SET_FROM_IMA_EXT (ZVKNHB);
- SET_FROM_IMA_EXT (ZVKSED);
- SET_FROM_IMA_EXT (ZVKSH);
- SET_FROM_IMA_EXT (ZVKT);
- SET_FROM_IMA_EXT (ZFH);
- SET_FROM_IMA_EXT (ZFHMIN);
- SET_FROM_IMA_EXT (ZIHINTNTL);
- SET_FROM_IMA_EXT (ZVFH);
- SET_FROM_IMA_EXT (ZVFHMIN);
- SET_FROM_IMA_EXT (ZFA);
- SET_FROM_IMA_EXT (ZTSO);
- SET_FROM_IMA_EXT (ZACAS);
- SET_FROM_IMA_EXT (ZICOND);
- /* Added since Linux v6.10. */
- SET_FROM_IMA_EXT (ZIHINTPAUSE);
- /* Added since Linux v6.11. */
- SET_FROM_IMA_EXT (ZVE32X);
- SET_FROM_IMA_EXT (ZVE32F);
- SET_FROM_IMA_EXT (ZVE64X);
- SET_FROM_IMA_EXT (ZVE64F);
- SET_FROM_IMA_EXT (ZVE64D);
- SET_FROM_IMA_EXT (ZIMOP);
- SET_FROM_IMA_EXT (ZCA);
- SET_FROM_IMA_EXT (ZCB);
- SET_FROM_IMA_EXT (ZCD);
- SET_FROM_IMA_EXT (ZCF);
- SET_FROM_IMA_EXT (ZCMOP);
- SET_FROM_IMA_EXT (ZAWRS);
- SET_FROM_IMA_EXT (SUPM);
- SET_FROM_IMA_EXT (ZICNTR);
- SET_FROM_IMA_EXT (ZIHPM);
- SET_FROM_IMA_EXT (ZFBFMIN);
- SET_FROM_IMA_EXT (ZVFBFMIN);
- SET_FROM_IMA_EXT (ZVFBFWMA);
- SET_FROM_IMA_EXT (ZICBOM);
- SET_FROM_IMA_EXT (ZAAMO);
- SET_FROM_IMA_EXT (ZALRSC);
- SET_FROM_IMA_EXT (ZABHA);
- SET_FROM_IMA_EXT (ZALASR);
- SET_FROM_IMA_EXT (ZICBOP);
- SET_FROM_IMA_EXT (ZILSD);
- SET_FROM_IMA_EXT (ZCLSD);
- SET_FROM_IMA_EXT (ZICFILP);
-
- const struct riscv_hwprobe hwprobe_ima_ext_1 = hwprobes[5];
- SET_FROM_IMA_EXT_1 (ZICFISS);
+#define RISCV_HWPROBE_EXT(NAME, UPPERCASE_NAME, KEY, BIT, XLEN)
\
+ if (riscv_hwprobe_value (hwprobes, npairs, KEY) & (1ULL << (BIT))) \
+ SET_EXT (UPPERCASE_NAME);
+#include "common/config/riscv/riscv-hwprobe.def"
for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; ++i)
__riscv_feature_bits.features[i] = features[i];
@@ -464,6 +286,8 @@ static void __init_riscv_features_bits_linux ()
static int __init = 0;
+void __init_riscv_feature_bits ();
+
void
__attribute__ ((constructor (101)))
__init_riscv_feature_bits ()
--
2.53.0
