> On 8/13/2026 11:54 PM, Jin Ma wrote: > > CACHE_ALIGNED_STD modeled a Veyron V1 store-commit optimization. That > > design will not reach silicon and no upstream tune enables the fusion. > > Remove the specialized recognizer and its unused flag. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-fusion.cc (riscv_fuse_cache_aligned_std): > > Remove. > > (riscv_fusion_table): Remove its entry. > > * config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Remove > > RISCV_FUSE_CACHE_ALIGNED_STD. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/fusion-cache-aligned-std.c: Remove. > > > > Signed-off-by: Jin Ma <[email protected]> > OK > jeff
Pushed to trunk. Thanks :) Jin
