Macro-fusion grouping only preserves pairs that are adjacent when
dependencies are built. Reorder the ready list to place an enabled
fusion partner after the last scheduled real instruction.
Search only the highest-priority window, reject candidates from a different
basic block, and leave every member of an existing scheduling group
untouched. Do not extend completed pairs or alter issue accounting. Keep
the positive tests as XFAIL until the tuning patch enables the pairs.
Static sched2 macro-fusion counts for SPEC CPU 2017 Integer built with
-O3 -flto, measured independently of scheduling priorities against a
baseline with xt-c9501fdvt fusion pairs enabled:
Benchmark Baseline With patch Change
500.perlbench_r 15302 15485 +1.2%
502.gcc_r 72806 73515 +1.0%
505.mcf_r 63 79 +25.4%
520.omnetpp_r 20479 21274 +3.9%
523.xalancbmk_r 42442 43132 +1.6%
525.x264_r 6232 6413 +2.9%
531.deepsjeng_r 299 305 +2.0%
541.leela_r 794 820 +3.3%
548.exchange2_r 353 384 +8.8%
557.xz_r 1217 1237 +1.6%
SUM 159987 162644 +1.7%
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_cached_can_issue_more): New scheduler
state.
(riscv_last_scheduled_insn): Likewise.
(riscv_last_fusion_insn_p): Likewise.
(riscv_sched_group_member_p): New function.
(riscv_sched_init): Initialize macro-fusion scheduler state.
(riscv_sched_variable_issue): Track fusion state within a basic block
and cache remaining issue capacity.
(riscv_sched_reorder_fusion): New function.
(riscv_sched_reorder): Try to place a fusion partner first and reset
the per-cycle issue count.
(riscv_sched_reorder2): New function.
(TARGET_SCHED_REORDER2): Define.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sched-reorder2-basic-block.c: New test.
* gcc.target/riscv/sched-reorder2-group.c: Likewise.
* gcc.target/riscv/sched-reorder2-load-pair.c: Likewise.
* gcc.target/riscv/sched-reorder2-postindex.c: Likewise.
* gcc.target/riscv/sched-reorder2-priority.c: Likewise.
Signed-off-by: Jin Ma <[email protected]>
---
gcc/config/riscv/riscv.cc | 137 ++++++++++++++++--
.../riscv/sched-reorder2-basic-block.c | 48 ++++++
.../gcc.target/riscv/sched-reorder2-group.c | 60 ++++++++
.../riscv/sched-reorder2-load-pair.c | 61 ++++++++
.../riscv/sched-reorder2-postindex.c | 42 ++++++
.../riscv/sched-reorder2-priority.c | 64 ++++++++
6 files changed, 398 insertions(+), 14 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/sched-reorder2-basic-block.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sched-reorder2-group.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sched-reorder2-load-pair.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sched-reorder2-postindex.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sched-reorder2-priority.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9f0c1d704c2..60303d84730 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11483,6 +11483,12 @@ struct last_vconfig
rtx avl;
} last_vconfig;
+/* Ready-list macro-fusion state for the current scheduling block. */
+
+static int riscv_cached_can_issue_more;
+static rtx_insn *riscv_last_scheduled_insn;
+static bool riscv_last_fusion_insn_p;
+
/* Clear LAST_VCONFIG so we have no known state. */
static void
clear_vconfig (void)
@@ -11526,15 +11532,28 @@ compatible_with_last_vconfig (rtx_insn *insn)
return true;
}
-/* Implement TARGET_SCHED_INIT, we use this to track the vector configuration
- of the last issued vector instruction. We can then use that information
- to potentially adjust the ready queue to issue instructions of a compatible
- vector configuration instead of a conflicting configuration. That will
- reduce the number of vsetvl instructions we ultimately emit. */
+/* Return true if INSN is part of an existing scheduling group. */
+
+static bool
+riscv_sched_group_member_p (rtx_insn *insn)
+{
+ if (SCHED_GROUP_P (insn))
+ return true;
+
+ rtx_insn *next = next_nonnote_nondebug_insn_bb (insn);
+ return next && INSN_P (next) && SCHED_GROUP_P (next);
+}
+
+/* Implement TARGET_SCHED_INIT. Track the vector configuration of the last
+ issued vector instruction so that reordering can reduce vsetvl instructions.
+ Also reset the ready-list fusion state for each scheduling block. */
static void
riscv_sched_init (FILE *, int, int)
{
clear_vconfig ();
+ riscv_cached_can_issue_more = riscv_issue_rate ();
+ riscv_last_scheduled_insn = NULL;
+ riscv_last_fusion_insn_p = false;
}
/* Implement TARGET_SCHED_VARIABLE_ISSUE. */
@@ -11542,16 +11561,38 @@ static int
riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
{
if (DEBUG_INSN_P (insn))
- return more;
+ {
+ riscv_cached_can_issue_more = more;
+ return more;
+ }
rtx_code code = GET_CODE (PATTERN (insn));
if (code == USE || code == CLOBBER)
- return more;
+ {
+ riscv_cached_can_issue_more = more;
+ return more;
+ }
+
+ bool fusion_p = riscv_sched_group_member_p (insn);
+ if (!fusion_p
+ && !sched_fusion
+ && riscv_last_scheduled_insn
+ && !riscv_last_fusion_insn_p
+ && (BLOCK_FOR_INSN (riscv_last_scheduled_insn)
+ == BLOCK_FOR_INSN (insn))
+ && riscv_get_fusion_pair_type (riscv_last_scheduled_insn, insn)
+ != RISCV_FUSE_NOTHING)
+ fusion_p = true;
+ riscv_last_fusion_insn_p = fusion_p;
+ riscv_last_scheduled_insn = insn;
/* GHOST insns are used for blockage and similar cases which
effectively end a cycle. */
if (get_attr_type (insn) == TYPE_GHOST)
- return 0;
+ {
+ riscv_cached_can_issue_more = 0;
+ return 0;
+ }
/* If we ever encounter an insn with an unknown type, trip
an assert so we can find and fix this problem. */
@@ -11585,17 +11626,73 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn
*insn, int more)
last_vconfig.ma = mask_agnostic_p (insn);
}
}
+ riscv_cached_can_issue_more = more - 1;
+ return riscv_cached_can_issue_more;
+}
- return more - 1;
+/* Move a fusion partner in the highest-priority window to the next slot
+ without disturbing existing scheduling groups. */
+
+static bool
+riscv_sched_reorder_fusion (FILE *file, int verbose, rtx_insn **ready,
+ int nready)
+{
+ if (sched_fusion
+ || sel_sched_p ()
+ || !riscv_macro_fusion_p ()
+ || !riscv_last_scheduled_insn
+ || riscv_last_fusion_insn_p
+ || nready == 0)
+ return false;
+
+ int priority = INSN_PRIORITY (ready[nready - 1]);
+ for (int i = nready - 1; i >= 0; --i)
+ {
+ rtx_insn *insn = ready[i];
+
+ if (INSN_PRIORITY (insn) < priority)
+ break;
+
+ if (riscv_sched_group_member_p (insn))
+ continue;
+
+ if (BLOCK_FOR_INSN (insn)
+ != BLOCK_FOR_INSN (riscv_last_scheduled_insn))
+ continue;
+
+ if (riscv_get_fusion_pair_type (riscv_last_scheduled_insn, insn)
+ == RISCV_FUSE_NOTHING)
+ continue;
+
+ if (i != nready - 1)
+ {
+ for (int j = i; j < nready - 1; ++j)
+ ready[j] = ready[j + 1];
+ ready[nready - 1] = insn;
+
+ if (verbose && file)
+ fprintf (file, ";;\t\tFusion reorder: (%d, %d)\n",
+ INSN_UID (riscv_last_scheduled_insn), INSN_UID (insn));
+ }
+ return true;
+ }
+
+ return false;
}
-/* Implement TARGET_SCHED_REORDER. The goal here is to look at the ready
- queue and reorder it ever so slightly to encourage issuing an insn with
- the same vector configuration as the most recently issued vector
- instruction. That will reduce vsetvl instructions. */
+/* Implement TARGET_SCHED_REORDER. Try to keep a macro-fusion pair adjacent
+ across a cycle boundary, then prefer an instruction with the same vector
+ configuration as the last issued vector instruction to reduce vsetvl
+ instructions. */
static int
-riscv_sched_reorder (FILE *, int, rtx_insn **ready, int *nreadyp, int)
+riscv_sched_reorder (FILE *file, int verbose, rtx_insn **ready,
+ int *nreadyp, int)
{
+ riscv_cached_can_issue_more = riscv_issue_rate ();
+
+ if (riscv_sched_reorder_fusion (file, verbose, ready, *nreadyp))
+ return riscv_cached_can_issue_more;
+
/* If we don't have a valid prior vector configuration, then there is
no point in reordering the ready queue, similarly if there is
just one entry in the queue. */
@@ -11641,7 +11738,16 @@ riscv_sched_reorder (FILE *, int, rtx_insn **ready,
int *nreadyp, int)
return riscv_issue_rate ();
}
+/* Implement TARGET_SCHED_REORDER2. */
+static int
+riscv_sched_reorder2 (FILE *file, int verbose, rtx_insn **ready,
+ int *nreadyp, int)
+{
+ if (riscv_cached_can_issue_more > 0)
+ riscv_sched_reorder_fusion (file, verbose, ready, *nreadyp);
+ return riscv_cached_can_issue_more;
+}
/* Return the set of fusible operations for the current tune. */
@@ -16637,6 +16743,9 @@ riscv_memtag_tag_bitsize ()
#undef TARGET_SCHED_REORDER
#define TARGET_SCHED_REORDER riscv_sched_reorder
+#undef TARGET_SCHED_REORDER2
+#define TARGET_SCHED_REORDER2 riscv_sched_reorder2
+
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost
diff --git a/gcc/testsuite/gcc.target/riscv/sched-reorder2-basic-block.c
b/gcc/testsuite/gcc.target/riscv/sched-reorder2-basic-block.c
new file mode 100644
index 00000000000..10d4b72417a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sched-reorder2-basic-block.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fsched2-use-superblocks -fdump-rtl-sched2-details" } */
+/* { dg-final { scan-rtl-dump-not {Fusion reorder: \(3, 6\)} "sched2" } } */
+
+/* Do not form a ready-list fusion pair across basic blocks. */
+
+long __RTL (startwith ("sched2"))
+test_reorder2_basic_block (void)
+{
+(function "test_reorder2_basic_block"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cnote 2 NOTE_INSN_FUNCTION_BEG)
+ (cinsn 3 (set (reg:DI a1)
+ (mem:DI (reg:DI a2) [0 S8 A64])))
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 4 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:DI a5)
+ (mem:DI (reg:DI t0) [0 S8 A64])))
+ (cinsn 6 (set (reg:DI a3)
+ (mem:DI
+ (plus:DI (reg:DI a2)
+ (const_int 8)) [0 S8 A64])))
+ (cinsn 7 (set (reg:DI a4)
+ (plus:DI (reg:DI a1) (reg:DI a0))))
+ (cinsn 8 (set (reg:DI a6)
+ (plus:DI (reg:DI a4) (reg:DI a0))))
+ (cinsn 9 (use (reg:DI a3)))
+ (cinsn 10 (use (reg:DI a5)))
+ (cinsn 11 (use (reg:DI a6)))
+ (cjump_insn 12 (simple_return))
+ (edge-to exit)
+ ) ;; block 3
+ (cbarrier 13)
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "test_reorder2_basic_block"
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sched-reorder2-group.c
b/gcc/testsuite/gcc.target/riscv/sched-reorder2-group.c
new file mode 100644
index 00000000000..b6f60d487a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sched-reorder2-group.c
@@ -0,0 +1,60 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
+/* { dg-final { scan-rtl-dump-times "macro fusion:" 2 "sched2" { xfail *-*-* }
} } */
+/* { dg-final { scan-rtl-dump-not {Fusion reorder: \(7, 5\)} "sched2" } } */
+
+/* Do not pair a load with the first instruction of an existing group. */
+
+long __RTL (startwith ("sched2"))
+test_reorder2_group (void)
+{
+(function "test_reorder2_group"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cnote 2 NOTE_INSN_FUNCTION_BEG)
+ (cinsn 3 (set (reg:DI a5)
+ (mem:DI (reg:DI t0) [0 S8 A64])))
+ (cinsn 4 (set (reg:DI a6)
+ (mem:DI
+ (plus:DI (reg:DI t0)
+ (const_int 8)) [0 S8 A64])))
+ (cinsn 5 (set (reg:DI a3)
+ (mem:DI
+ (plus:DI (reg:DI a2)
+ (const_int 8)) [0 S8 A64])))
+ (cinsn 6 (set (reg:DI a4)
+ (mem:DI
+ (plus:DI (reg:DI a2)
+ (const_int 16)) [0 S8 A64])))
+ (cinsn 7 (set (reg:DI a1)
+ (mem:DI (reg:DI a2) [0 S8 A64])))
+ (cinsn 8 (set (reg:DI a7)
+ (plus:DI (reg:DI a1) (reg:DI a0))))
+ (cinsn 9 (set (reg:DI t1)
+ (plus:DI (reg:DI a7) (reg:DI a0))))
+ (cinsn 10 (set (reg:DI t2)
+ (plus:DI (reg:DI t1) (reg:DI a0))))
+ (cinsn 11 (set (reg:DI t3)
+ (plus:DI (reg:DI t2) (reg:DI a0))))
+ (cinsn 12 (set (reg:DI t4)
+ (plus:DI (reg:DI t3) (reg:DI a0))))
+ (cinsn 13 (use (reg:DI t4)))
+ (cinsn 14 (use (reg:DI a3)))
+ (cinsn 15 (use (reg:DI a4)))
+ (cinsn 16 (use (reg:DI a5)))
+ (cinsn 17 (use (reg:DI a6)))
+ (cjump_insn 18 (simple_return))
+ (edge-to exit)
+ ) ;; block 2
+ (cbarrier 19)
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "test_reorder2_group"
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sched-reorder2-load-pair.c
b/gcc/testsuite/gcc.target/riscv/sched-reorder2-load-pair.c
new file mode 100644
index 00000000000..7bb737210f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sched-reorder2-load-pair.c
@@ -0,0 +1,61 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-rtl-dump-times {Fusion reorder: \(3, 5\)} 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-not "macro fusion:" "sched2" } } */
+
+/* Move the second A2 load next to the first without extending the pair. */
+
+/*
+**test_reorder2_load_pair: { xfail *-*-* }
+** ld a1,0\(a2\)
+** ld a3,8\(a2\)
+** ld a5,0\(a0\)
+** ld a6,0\(t0\)
+** ld a4,16\(a2\)
+** ...
+** ret
+*/
+long __RTL (startwith ("sched2"))
+test_reorder2_load_pair (void)
+{
+(function "test_reorder2_load_pair"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cnote 2 NOTE_INSN_FUNCTION_BEG)
+ (cinsn 3 (set (reg:DI a1)
+ (mem:DI (reg:DI a2) [0 S8 A64])))
+ (cinsn 4 (set (reg:DI a5)
+ (mem:DI (reg:DI a0) [0 S8 A64])))
+ (cinsn 5 (set (reg:DI a3)
+ (mem:DI
+ (plus:DI (reg:DI a2)
+ (const_int 8)) [0 S8 A64])))
+ (cinsn 6 (set (reg:DI a6)
+ (mem:DI (reg:DI t0) [0 S8 A64])))
+ (cinsn 7 (set (reg:DI a4)
+ (mem:DI
+ (plus:DI (reg:DI a2)
+ (const_int 16)) [0 S8 A64])))
+ (cinsn 8 (set (reg:DI a7)
+ (plus:DI (reg:DI a1) (reg:DI a0))))
+ (cinsn 9 (use (reg:DI a7)))
+ (cinsn 10 (use (reg:DI a3)))
+ (cinsn 11 (use (reg:DI a4)))
+ (cinsn 12 (use (reg:DI a5)))
+ (cinsn 13 (use (reg:DI a6)))
+ (cjump_insn 14 (simple_return))
+ (edge-to exit)
+ ) ;; block 2
+ (cbarrier 15)
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "test_reorder2_load_pair"
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sched-reorder2-postindex.c
b/gcc/testsuite/gcc.target/riscv/sched-reorder2-postindex.c
new file mode 100644
index 00000000000..737f4f6cc69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sched-reorder2-postindex.c
@@ -0,0 +1,42 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-rtl-dump-times {Fusion reorder: \(3, 5\)} 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-not "macro fusion:" "sched2" } } */
+
+/* Recognize POSTINDEX_ST across a zero-cost USE. */
+
+/*
+**test_reorder2_postindex_st: { xfail *-*-* }
+** sd a2,0\(a0\)
+** addi a0,a0,8
+** ret
+*/
+long __RTL (startwith ("sched2"))
+test_reorder2_postindex_st (void)
+{
+(function "test_reorder2_postindex_st"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cnote 2 NOTE_INSN_FUNCTION_BEG)
+ (cinsn 3 (set (mem:DI (reg:DI a0) [0 S8 A64])
+ (reg:DI a2)))
+ (cinsn 4 (use (reg:DI a6)))
+ (cinsn 5 (set (reg:DI a0)
+ (plus:DI (reg:DI a0) (const_int 8))))
+ (cinsn 6 (use (reg:DI a0)))
+ (cjump_insn 7 (simple_return))
+ (edge-to exit)
+ ) ;; block 2
+ (cbarrier 8)
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "test_reorder2_postindex_st"
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sched-reorder2-priority.c
b/gcc/testsuite/gcc.target/riscv/sched-reorder2-priority.c
new file mode 100644
index 00000000000..8d9c05e2731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sched-reorder2-priority.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-rtl-dump-not "Fusion reorder:" "sched2" } } */
+
+/* Do not move a lower-priority fusion candidate ahead of the ADD. */
+
+/*
+**test_reorder2_respects_priority:
+** ld a1,0\(a2\)
+** add a3,a4,a5
+** ld a6,8\(a2\)
+** ...
+** ret
+*/
+long __RTL (startwith ("sched2"))
+test_reorder2_respects_priority (void)
+{
+(function "test_reorder2_respects_priority"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cnote 2 NOTE_INSN_FUNCTION_BEG)
+ (cinsn 3 (set (reg:DI a1)
+ (mem:DI (reg:DI a2) [0 S8 A64])))
+ (cinsn 4 (set (reg:DI a3)
+ (plus:DI (reg:DI a4) (reg:DI a5))))
+ (cinsn 5 (set (reg:DI a6)
+ (mem:DI
+ (plus:DI (reg:DI a2)
+ (const_int 8)) [0 S8 A64])))
+ (cinsn 6 (set (reg:DI a7)
+ (plus:DI (reg:DI a1) (reg:DI a0))))
+ (cinsn 7 (set (reg:DI t0)
+ (plus:DI (reg:DI a7) (reg:DI a0))))
+ (cinsn 8 (set (reg:DI t1)
+ (plus:DI (reg:DI t0) (reg:DI a0))))
+ (cinsn 9 (set (reg:DI t2)
+ (plus:DI (reg:DI a3) (reg:DI a0))))
+ (cinsn 10 (set (reg:DI t3)
+ (plus:DI (reg:DI t2) (reg:DI a0))))
+ (cinsn 11 (set (reg:DI t4)
+ (plus:DI (reg:DI t3) (reg:DI a0))))
+ (cinsn 12 (set (reg:DI t5)
+ (plus:DI (reg:DI t4) (reg:DI a0))))
+ (cinsn 13 (set (reg:DI t6)
+ (plus:DI (reg:DI t5) (reg:DI a0))))
+ (cinsn 14 (use (reg:DI t1)))
+ (cinsn 15 (use (reg:DI t6)))
+ (cinsn 16 (use (reg:DI a6)))
+ (cjump_insn 17 (simple_return))
+ (edge-to exit)
+ ) ;; block 2
+ (cbarrier 18)
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "test_reorder2_respects_priority"
+}
--
2.52.0
