Models that have hardware prefetchers prefer sorted store instructions.
The autoprefetcher model is based on that of AArch64. We start with
only AUTOPREFETCHER_OFF and AUTOPREFETCHER_WEAK, leaving the strong
model for further work. The support of a strong model is only useful
after max_issue is supported. It is little work to implement one like
Arm's, but some research may need to be done of its benefits.
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_tune_param): New member.
(xt_c9501_tune_info): Set autoprefetcher model to weak.
(riscv_override_options_internal): Set
param_sched_autopref_queue_depth based on autoprefetcher model.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/autopref-xt-c9501fdvt.c: New test.
---
gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
.../gcc.target/riscv/autopref-xt-c9501fdvt.c | 13 +++++++++++
2 files changed, 35 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/autopref-xt-c9501fdvt.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a2a51c019ec..7c061614aa5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -305,6 +305,11 @@ struct riscv_tune_param
unsigned short vec_reassoc_width = 1;
unsigned int small_loop_unroll_ninsns = 4;
unsigned int small_loop_unroll_factor = 2;
+ enum riscv_autoprefetch_model
+ {
+ AUTOPREFETCHER_OFF,
+ AUTOPREFETCHER_WEAK
+ } autoprefetcher_model = AUTOPREFETCHER_OFF;
};
@@ -747,6 +752,7 @@ static const struct riscv_tune_param xt_c9501_tune_info = {
1, /* vec_reassoc_width. */
4, /* small_loop_unroll_ninsns. */
8, /* small_loop_unroll_factor. */
+ riscv_tune_param::AUTOPREFETCHER_WEAK, /* autoprefetcher_model */
};
/* Costs to use when optimizing for Tenstorrent Ascalon 8 wide. */
@@ -12195,6 +12201,22 @@ riscv_override_options_internal (struct gcc_options
*opts)
opts->x_flag_cf_protection
= (cf_protection_level) (opts->x_flag_cf_protection | CF_SET);
}
+
+ int queue_depth = 0;
+ switch (cpu->tune_param->autoprefetcher_model)
+ {
+ case riscv_tune_param::AUTOPREFETCHER_OFF:
+ queue_depth = -1;
+ break;
+ case riscv_tune_param::AUTOPREFETCHER_WEAK:
+ queue_depth = 0;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+ param_sched_autopref_queue_depth, queue_depth);
}
/* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
diff --git a/gcc/testsuite/gcc.target/riscv/autopref-xt-c9501fdvt.c
b/gcc/testsuite/gcc.target/riscv/autopref-xt-c9501fdvt.c
new file mode 100644
index 00000000000..c506b0d6fbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/autopref-xt-c9501fdvt.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt" } */
+
+void
+foo(long *a)
+{
+ a[2] = 1;
+ a[1] = 1;
+ a[0] = 1;
+}
+
+/* { dg-final { scan-assembler
"sd.*0\\(a0\\)\n\\s*sd.*8\\(a0\\)\n\\s*sd.*16\\(a0\\)" } } */
--
2.46.0
