On 8/21/2026 3:32 AM, Bohan Lei wrote:
Models that have hardware prefetchers prefer sorted store instructions.
The autoprefetcher model is based on that of AArch64. We start with
only AUTOPREFETCHER_OFF and AUTOPREFETCHER_WEAK, leaving the strong
model for further work. The support of a strong model is only useful
after max_issue is supported. It is little work to implement one like
Arm's, but some research may need to be done of its benefits.
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_tune_param): New member.
(xt_c9501_tune_info): Set autoprefetcher model to weak.
(riscv_override_options_internal): Set
param_sched_autopref_queue_depth based on autoprefetcher model.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/autopref-xt-c9501fdvt.c: New test.
Yea, I have a long term TODO to investigate this space. We had a local
hack in our spec builds for adjusting the autoprefetch queue depth that
I inherited. No explanation or anything (and predates putting those
config files in git for internal work). I tried to rip it out a while
back and did see meaningful performance deltas, but never had the time
to dive into those performance differences.
Anyway, this patch is OK for the trunk. THanks.
Jeff
