commit f2609a4c653a4993eec7ed9a2ad05caf936f0178
Author: Roger Sayle <[email protected]>
Date: Sat May 16 08:44:06 2026 +0100
x86_64: Handle hard registers in TImode STV with inter-unit moves.
checks TARGET_AVX for vpinsrq and vpextrq. But pinsrq and pextrq are
added in SSE4_1. Check TARGET_SSE4_1 instead of TARGET_AVX for pinsrq
and pextrq.
gcc/
PR target/127020
* config/i386/i386-features.cc
(timode_scalar_chain::compute_convert_gain): Check TARGET_SSE4_1
instead of TARGET_AVX for pinsrq and pextrq.
gcc/testsuite/
PR target/127020
* gcc.target/i386/sse4_1-stv-14.c: New test.
--
H.J.
From edf50dfb097d8df0c08a1d8946b055d79becf529 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <[email protected]>
Date: Mon, 24 Aug 2026 19:32:30 +0800
Subject: [PATCH] x86-64: Check SSE4.1 for pinsrq/pextrq in TImode STV
commit f2609a4c653a4993eec7ed9a2ad05caf936f0178
Author: Roger Sayle <[email protected]>
Date: Sat May 16 08:44:06 2026 +0100
x86_64: Handle hard registers in TImode STV with inter-unit moves.
checks TARGET_AVX for vpinsrq and vpextrq. But pinsrq and pextrq are
added in SSE4_1. Check TARGET_SSE4_1 instead of TARGET_AVX for pinsrq
and pextrq.
gcc/
PR target/127020
* config/i386/i386-features.cc
(timode_scalar_chain::compute_convert_gain): Check TARGET_SSE4_1
instead of TARGET_AVX for pinsrq and pextrq.
gcc/testsuite/
PR target/127020
* gcc.target/i386/sse4_1-stv-14.c: New test.
Signed-off-by: H.J. Lu <[email protected]>
---
gcc/config/i386/i386-features.cc | 8 ++++----
gcc/testsuite/gcc.target/i386/sse4_1-stv-14.c | 15 +++++++++++++++
2 files changed, 19 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-stv-14.c
diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index 65e1fe16143..eb5f82e42cb 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -1677,8 +1677,8 @@ timode_scalar_chain::compute_convert_gain ()
case REG:
if (GENERAL_REGNO_P (REGNO (src)))
{
- if (TARGET_AVX)
- /* vmovq + vpinsrq */
+ if (TARGET_SSE4_1)
+ /* movq + pinsrq */
igain = speed_p ? -ix86_cost->integer_to_sse
- COSTS_N_INSNS (1)
: -COSTS_N_BYTES (11);
@@ -1690,8 +1690,8 @@ timode_scalar_chain::compute_convert_gain ()
}
else if (GENERAL_REG_P (dst))
{
- if (TARGET_AVX)
- /* vpextrq + vmovq */
+ if (TARGET_SSE4_1)
+ /* pextrq + movq */
igain = speed_p ? -ix86_cost->sse_to_integer
- COSTS_N_INSNS (1)
: -COSTS_N_BYTES (11);
diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-stv-14.c b/gcc/testsuite/gcc.target/i386/sse4_1-stv-14.c
new file mode 100644
index 00000000000..e9e1363da9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse4_1-stv-14.c
@@ -0,0 +1,15 @@
+/* PR target/127020. */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2 -march=x86-64-v2" } */
+
+extern __int128 a, b, c, z;
+
+__int128
+func (__int128 x)
+{
+ return (x ^ a ^ b ^ c ^ z);
+}
+
+/* { dg-final { scan-assembler-times "pxor" 4 } } */
+/* { dg-final { scan-assembler-times "pinsrq" 1 } } */
+/* { dg-final { scan-assembler-times "pextrq" 1 } } */
--
2.55.0
