Copying an address into a fixed-length vector can expand to
(set (reg:V2SI ...)
(subreg:V2SI (symbol_ref:DI (...)) 0))
The RVV move patterns require register or memory operands and do not
accept a SUBREG whose inner operand is a constant. This leaves an
unrecognizable insn that ICEs during the vregs pass.
In riscv_vector::legitimize_move, force the inner constant into a
register and rebuild the SUBREG before emitting the vector move.
This follows the approach used by ix86_expand_vector_move for SUBREGs
of constants: materialize the inner constant first, then rebuild the
SUBREG.
PR target/127060
gcc/ChangeLog:
* config/riscv/riscv-v.cc (legitimize_move): Force the inner
constant of a SUBREG into a register.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr127060.c: New test.
Reported-by: XChy <[email protected]>
Signed-off-by: Jin Ma <[email protected]>
---
gcc/config/riscv/riscv-v.cc | 13 +++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/pr127060.c | 14 ++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127060.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index bec1c9ebaec..f605be13ab2 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1883,6 +1883,19 @@ legitimize_move (rtx dest, rtx *srcp)
return true;
}
+ /* A SUBREG of a constant is not a valid vector move operand. Force the
+ inner constant into a register and rebuild the SUBREG. */
+ if (SUBREG_P (src)
+ && CONSTANT_P (SUBREG_REG (src))
+ && can_create_pseudo_p ())
+ {
+ machine_mode inner_mode = GET_MODE (SUBREG_REG (src));
+ rtx inner = force_reg (inner_mode, SUBREG_REG (src));
+ src = simplify_gen_subreg (mode, inner, inner_mode, SUBREG_BYTE (src));
+ gcc_assert (src);
+ *srcp = src;
+ }
+
/* The canonical way of extracting vectors from vectors is the vec_extract
optab with appropriate source and dest modes. This is rather a VLS style
approach, though as we would need to enumerate all dest modes that are
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127060.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127060.c
new file mode 100644
index 00000000000..43fe619f8d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127060.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */
+/* PR target/127060 */
+
+typedef int v2si __attribute__ ((vector_size (8)));
+
+int
+f (unsigned long i)
+{
+ v2si v;
+ int (*p) (unsigned long) = f;
+ __builtin_memcpy (&v, &p, sizeof (p));
+ return v[i & 1];
+}
--
2.52.0
