From: Pan Li <[email protected]>
Add test cases for register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c: New
test.
Signed-off-by: Pan Li <[email protected]>
---
.../autovec/group_overlap/vwmaccu_vx-u16-m1.c | 58 +++++++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u16-m2.c | 50 ++++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u16-m4.c | 46 +++++++++++++++
.../group_overlap/vwmaccu_vx-u16-mf2.c | 21 +++++++
.../group_overlap/vwmaccu_vx-u16-mf4.c | 21 +++++++
.../autovec/group_overlap/vwmaccu_vx-u32-m1.c | 58 +++++++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u32-m2.c | 50 ++++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u32-m4.c | 46 +++++++++++++++
.../group_overlap/vwmaccu_vx-u32-mf2.c | 21 +++++++
.../autovec/group_overlap/vwmaccu_vx-u8-m1.c | 58 +++++++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u8-m2.c | 50 ++++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u8-m4.c | 46 +++++++++++++++
.../autovec/group_overlap/vwmaccu_vx-u8-mf2.c | 21 +++++++
.../autovec/group_overlap/vwmaccu_vx-u8-mf4.c | 21 +++++++
.../autovec/group_overlap/vwmaccu_vx-u8-mf8.c | 21 +++++++
15 files changed, 588 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c
new file mode 100644
index 00000000000..3336bc855c3
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e16m1,
+ vuint16m1_t,
+ vuint32m2_t,
+ uint16_t,
+ __riscv_vle16_v_u16m1,
+ __riscv_vle32_v_u32m2,
+ __riscv_vwmaccu_vx_u32m2,
+ __riscv_vse32_v_u32m2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e16m1,
+ vuint16m1_t,
+ vuint32m2_t,
+ vuint16m2_t,
+ uint16_t,
+ __riscv_vle32_v_u32m2,
+ __riscv_vreinterpret_v_u32m2_u16m2,
+ __riscv_vget_v_u16m2_u16m1,
+ __riscv_vwmaccu_vx_u32m2,
+ __riscv_vse32_v_u32m2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v6,s0,v27([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,s0,v26([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v14,s0,v31([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v12,s0,v30([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,s0,v25([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v26,s0,v24([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v10,s0,v29([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v30,s0,v23([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,s0,v22([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,s0,v28([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v26,s0,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,s0,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v22,s0,v21([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,s0,v18([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v20,s0,v19([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v18,s0,v1([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v5([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c
new file mode 100644
index 00000000000..cc417722569
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e16m2,
+ vuint16m2_t,
+ vuint32m4_t,
+ uint16_t,
+ __riscv_vle16_v_u16m2,
+ __riscv_vle32_v_u32m4,
+ __riscv_vwmaccu_vx_u32m4,
+ __riscv_vse32_v_u32m4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e16m2,
+ vuint16m2_t,
+ vuint32m4_t,
+ vuint16m4_t,
+ uint16_t,
+ __riscv_vle32_v_u32m4,
+ __riscv_vreinterpret_v_u32m4_u16m4,
+ __riscv_vget_v_u16m4_u16m2,
+ __riscv_vwmaccu_vx_u32m4,
+ __riscv_vse32_v_u32m4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v12,a2,v30([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v28([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v26([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,a2,v24([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,a2,v22([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,a2,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v20,a2,v2([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v10([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c
new file mode 100644
index 00000000000..feaf66e83fa
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-m4.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e16m4,
+ vuint16m4_t,
+ vuint32m8_t,
+ uint16_t,
+ __riscv_vle16_v_u16m4,
+ __riscv_vle32_v_u32m8,
+ __riscv_vwmaccu_vx_u32m8,
+ __riscv_vse32_v_u32m8,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e16m4,
+ vuint16m4_t,
+ vuint32m8_t,
+ vuint16m8_t,
+ uint16_t,
+ __riscv_vle32_v_u32m8,
+ __riscv_vreinterpret_v_u32m8_u16m8,
+ __riscv_vget_v_u16m8_u16m4,
+ __riscv_vwmaccu_vx_u32m8,
+ __riscv_vse32_v_u32m8,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,a2,v12([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v8([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v4([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c
new file mode 100644
index 00000000000..582d5ecab1c
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e16m1,
+ vuint16mf2_t,
+ vuint32m1_t,
+ uint16_t,
+ __riscv_vle16_v_u16mf2,
+ __riscv_vle32_v_u32m1,
+ __riscv_vwmaccu_vx_u32m1,
+ __riscv_vse32_v_u32m1,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+ register group must not overlap the source at all. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx} 16 } } */
+/* { dg-final { scan-assembler-not
{vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c
new file mode 100644
index 00000000000..8fe1ecb728a
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u16-mf4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e16m1,
+ vuint16mf4_t,
+ vuint32mf2_t,
+ uint16_t,
+ __riscv_vle16_v_u16mf4,
+ __riscv_vle32_v_u32mf2,
+ __riscv_vwmaccu_vx_u32mf2,
+ __riscv_vse32_v_u32mf2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+ register group must not overlap the source at all. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx} 16 } } */
+/* { dg-final { scan-assembler-not
{vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c
new file mode 100644
index 00000000000..985bcfd2fb8
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e32m1,
+ vuint32m1_t,
+ vuint64m2_t,
+ uint32_t,
+ __riscv_vle32_v_u32m1,
+ __riscv_vle64_v_u64m2,
+ __riscv_vwmaccu_vx_u64m2,
+ __riscv_vse64_v_u64m2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e32m1,
+ vuint32m1_t,
+ vuint64m2_t,
+ vuint32m2_t,
+ uint32_t,
+ __riscv_vle64_v_u64m2,
+ __riscv_vreinterpret_v_u64m2_u32m2,
+ __riscv_vget_v_u32m2_u32m1,
+ __riscv_vwmaccu_vx_u64m2,
+ __riscv_vse64_v_u64m2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v6,s0,v27([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,s0,v26([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v14,s0,v31([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v12,s0,v30([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,s0,v25([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v26,s0,v24([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v10,s0,v29([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v30,s0,v23([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,s0,v22([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,s0,v28([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v26,s0,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,s0,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v22,s0,v21([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,s0,v18([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v20,s0,v19([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v18,s0,v1([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v5([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c
new file mode 100644
index 00000000000..d10f2a3d4eb
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e32m2,
+ vuint32m2_t,
+ vuint64m4_t,
+ uint32_t,
+ __riscv_vle32_v_u32m2,
+ __riscv_vle64_v_u64m4,
+ __riscv_vwmaccu_vx_u64m4,
+ __riscv_vse64_v_u64m4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e32m2,
+ vuint32m2_t,
+ vuint64m4_t,
+ vuint32m4_t,
+ uint32_t,
+ __riscv_vle64_v_u64m4,
+ __riscv_vreinterpret_v_u64m4_u32m4,
+ __riscv_vget_v_u32m4_u32m2,
+ __riscv_vwmaccu_vx_u64m4,
+ __riscv_vse64_v_u64m4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v12,a2,v30([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v28([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v26([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,a2,v24([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,a2,v22([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,a2,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v20,a2,v2([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v10([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c
new file mode 100644
index 00000000000..f5962ca7e53
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-m4.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e32m4,
+ vuint32m4_t,
+ vuint64m8_t,
+ uint32_t,
+ __riscv_vle32_v_u32m4,
+ __riscv_vle64_v_u64m8,
+ __riscv_vwmaccu_vx_u64m8,
+ __riscv_vse64_v_u64m8,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e32m4,
+ vuint32m4_t,
+ vuint64m8_t,
+ vuint32m8_t,
+ uint32_t,
+ __riscv_vle64_v_u64m8,
+ __riscv_vreinterpret_v_u64m8_u32m8,
+ __riscv_vget_v_u32m8_u32m4,
+ __riscv_vwmaccu_vx_u64m8,
+ __riscv_vse64_v_u64m8,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,a2,v12([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v8([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v4([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c
new file mode 100644
index 00000000000..5d5e84e0a2f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u32-mf2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e32m1,
+ vuint32mf2_t,
+ vuint64m1_t,
+ uint32_t,
+ __riscv_vle32_v_u32mf2,
+ __riscv_vle64_v_u64m1,
+ __riscv_vwmaccu_vx_u64m1,
+ __riscv_vse64_v_u64m1,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+ register group must not overlap the source at all. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx} 16 } } */
+/* { dg-final { scan-assembler-not
{vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c
new file mode 100644
index 00000000000..5e60f4338d3
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e8m1,
+ vuint8m1_t,
+ vuint16m2_t,
+ uint8_t,
+ __riscv_vle8_v_u8m1,
+ __riscv_vle16_v_u16m2,
+ __riscv_vwmaccu_vx_u16m2,
+ __riscv_vse16_v_u16m2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e8m1,
+ vuint8m1_t,
+ vuint16m2_t,
+ vuint8m2_t,
+ uint8_t,
+ __riscv_vle16_v_u16m2,
+ __riscv_vreinterpret_v_u16m2_u8m2,
+ __riscv_vget_v_u8m2_u8m1,
+ __riscv_vwmaccu_vx_u16m2,
+ __riscv_vse16_v_u16m2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v6,s0,v27([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,s0,v26([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v14,s0,v31([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v12,s0,v30([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,s0,v25([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v26,s0,v24([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v10,s0,v29([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v30,s0,v23([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,s0,v22([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,s0,v28([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v26,s0,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,s0,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v22,s0,v21([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,s0,v18([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v20,s0,v19([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v18,s0,v1([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v5([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c
new file mode 100644
index 00000000000..be5d8f9e094
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e8m2,
+ vuint8m2_t,
+ vuint16m4_t,
+ uint8_t,
+ __riscv_vle8_v_u8m2,
+ __riscv_vle16_v_u16m4,
+ __riscv_vwmaccu_vx_u16m4,
+ __riscv_vse16_v_u16m4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e8m2,
+ vuint8m2_t,
+ vuint16m4_t,
+ vuint8m4_t,
+ uint8_t,
+ __riscv_vle16_v_u16m4,
+ __riscv_vreinterpret_v_u16m4_u8m4,
+ __riscv_vget_v_u8m4_u8m2,
+ __riscv_vwmaccu_vx_u16m4,
+ __riscv_vse16_v_u16m4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v12,a2,v30([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v28([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v26([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,a2,v24([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,a2,v22([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v28,a2,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v20,a2,v2([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v10([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c
new file mode 100644
index 00000000000..00c64ce4393
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-m4.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e8m4,
+ vuint8m4_t,
+ vuint16m8_t,
+ uint8_t,
+ __riscv_vle8_v_u8m4,
+ __riscv_vle16_v_u16m8,
+ __riscv_vwmaccu_vx_u16m8,
+ __riscv_vse16_v_u16m8,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4)
+
+DEF_GROUP_OVERLAP_TERNARY_5(
+ __riscv_vsetvlmax_e8m4,
+ vuint8m4_t,
+ vuint16m8_t,
+ vuint8m8_t,
+ uint8_t,
+ __riscv_vle16_v_u16m8,
+ __riscv_vreinterpret_v_u16m8_u8m8,
+ __riscv_vget_v_u8m8_u8m4,
+ __riscv_vwmaccu_vx_u16m8,
+ __riscv_vse16_v_u16m8,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2)
+
+/* ternary_4: the accumulator occupies the whole destination register group and
+ is live when the narrowed source is read, so the source cannot be allocated
+ inside the destination register group. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v24,a2,v12([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v8([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v4([^0-9]|$)} 1 } }
*/
+
+/* ternary_5: the narrowed source is the highest-numbered half of its own
+ accumulator, thus it overlaps the highest-numbered part of the destination
+ register group. Without the group overlap the source would have to be
+ copied out to a disjoint register group first. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v16,a2,v20([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c
new file mode 100644
index 00000000000..a93fa986430
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e8m1,
+ vuint8mf2_t,
+ vuint16m1_t,
+ uint8_t,
+ __riscv_vle8_v_u8mf2,
+ __riscv_vle16_v_u16m1,
+ __riscv_vwmaccu_vx_u16m1,
+ __riscv_vse16_v_u16m1,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+ register group must not overlap the source at all. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx} 16 } } */
+/* { dg-final { scan-assembler-not
{vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c
new file mode 100644
index 00000000000..398b525e82d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e8m1,
+ vuint8mf4_t,
+ vuint16mf2_t,
+ uint8_t,
+ __riscv_vle8_v_u8mf4,
+ __riscv_vle16_v_u16mf2,
+ __riscv_vwmaccu_vx_u16mf2,
+ __riscv_vse16_v_u16mf2,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+ register group must not overlap the source at all. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx} 16 } } */
+/* { dg-final { scan-assembler-not
{vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c
new file mode 100644
index 00000000000..1eee6d40fab
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx-u8-mf8.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_TERNARY_4(
+ __riscv_vsetvlmax_e8m1,
+ vuint8mf8_t,
+ vuint16mf4_t,
+ uint8_t,
+ __riscv_vle8_v_u8mf8,
+ __riscv_vle16_v_u16mf4,
+ __riscv_vwmaccu_vx_u16mf4,
+ __riscv_vse16_v_u16mf4,
+ vwmaccu_vx,
+ LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+ register group must not overlap the source at all. */
+/* { dg-final { scan-assembler-times {vwmaccu\.vx} 16 } } */
+/* { dg-final { scan-assembler-not
{vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */
--
2.43.0
