AMD General Hi Haochen,
> -----Original Message----- > From: Haochen Jiang <[email protected]> > Sent: 19 August 2026 11:19 > To: [email protected] > Cc: [email protected]; [email protected]; Kumar, Venkataramanan > <[email protected]>; Sharma, Dipesh > <[email protected]>; Sharma, Dipesh <[email protected]> > Subject: [PATCH v2 1/7] Initial support for ACEv1 > > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. > > > ACEv1 is a new ISA documented here: > > https://x86ecosystem.org/resource/ai-compute-extensions-ace-specification/ > > In this patch, we will first add initial support for ACEv1. The instruction > support will come afterwards. > > gcc/ChangeLog: > > * common/config/i386/cpuinfo.h > (get_available_features): Add ACEV1. > * common/config/i386/i386-common.cc > (OPTION_MASK_ISA2_ACEV1_SET): New. > (OPTION_MASK_ISA2_AVX10V2AUX_UNSET): Disable ACEV1. > (OPTION_MASK_ISA2_ACEV1_UNSET): New. > (ix86_handle_option): Handle ACEV1. > * common/config/i386/i386-cpuinfo.h > (enum processor_features): Add FEATURE_ACEV1. > * common/config/i386/i386-isas.h: Handle acev1. > * config/i386/cpuid.h (bit_ACE): New. > * config/i386/i386-c.cc (ix86_target_macros_internal): > Handle acev1. > * config/i386/i386-isa.def (ACEV1): Add DEF_PTA. > * config/i386/i386-options.cc (isa2_opts): Handle acev1. > (ix86_valid_target_attribute_inner_p): Ditto. > * config/i386/i386.opt: Add macev1. > * config/i386/i386.opt.urls: Regenerated. > * doc/extend.texi: Add acev1 documentation. > * doc/invoke.texi: Ditto. > * doc/sourcebuild.texi: Ditto. > > Co-authored-by: Dipesh Sharma <[email protected]> > --- > gcc/common/config/i386/cpuinfo.h | 33 ++++++++++++++++- > gcc/common/config/i386/i386-common.cc | 22 +++++++++++- > gcc/common/config/i386/i386-cpuinfo.h | 1 + > gcc/common/config/i386/i386-isas.h | 1 + > gcc/config/i386/cpuid.h | 3 ++ > gcc/config/i386/i386-c.cc | 2 ++ > gcc/config/i386/i386-isa.def | 1 + > gcc/config/i386/i386-options.cc | 4 ++- > gcc/config/i386/i386.opt | 5 +++ > gcc/config/i386/i386.opt.urls | 3 ++ > gcc/doc/extend.texi | 5 +++ > gcc/doc/invoke.texi | 8 ++++- > gcc/doc/sourcebuild.texi | 51 ++++++++++++++------------- > 13 files changed, 111 insertions(+), 28 deletions(-) > > diff --git a/gcc/common/config/i386/cpuinfo.h > b/gcc/common/config/i386/cpuinfo.h > index fef8f90f94c..c63349085c0 100644 > --- a/gcc/common/config/i386/cpuinfo.h > +++ b/gcc/common/config/i386/cpuinfo.h > @@ -822,6 +822,7 @@ get_available_features (struct __processor_model > *cpu_model, > int has_kl = 0; > /* Record AVX10 version. */ > int avx10_set = 0; > + int ace_set = 0, avx10v2aux_set = 0; > int version = 0; > if ((ecx & bit_OSXSAVE)) Since we have XSAVE BSR state as a part of ACE detection algorithm, should we also check for OSXSAVE state here just like what exist for AMX ? <Snip start> 1. ( AVX10.1 and AVX10_V1_AUX ) or AVX10.2 2. AVX10_V2_AUX 3. ACE 4. ACE_VSN >= 1 5. XCR0[20,18:17] = 0b111 (XSAVE state enabled for tile + BSR) 6. XCR0[7:5] = 0b111 <Snip end> > { > @@ -1045,6 +1046,11 @@ get_available_features (struct __processor_model > *cpu_model, > if (edx & bit_AVX10) > avx10_set = 1; > } > + if (avx10_set) > + { > + if (ecx & bit_ACE) > + ace_set = 1; > + } > if (amx_usable) > { > if (eax & bit_AMX_FP16) > @@ -1143,7 +1149,32 @@ get_available_features (struct __processor_model > *cpu_model, > { > __cpuid_count (0x24, 1, eax, ebx, ecx, edx); > if (ecx & bit_AVX10V2AUX) > - set_feature (FEATURE_AVX10V2AUX); > + { > + set_feature (FEATURE_AVX10V2AUX); > + avx10v2aux_set = 1; > + } > + } > + } > + > + /* Get Advanced Features at level 0x1d (eax = 0x1d). > + ACE check must be put after AVX10 check to get AVX10 features. > + TODO: Change the condition after AVX10V1AUX is added. */ if > + (version >= 2 && avx10v2aux_set && ace_set && max_cpuid_level >= 0x1d) Should this guard also have ace_usable set after we check for ACE OSXSAVE bits? > + { > + __cpuid_count (0x1d, 0, eax, ebx, ecx, edx); > + if (eax == 2) > + { > + __cpuid_count (0x1d, 2, eax, ebx, ecx, edx); > + version = eax & 0xff; > + switch (version) > + { > + case 1: > + set_feature (FEATURE_ACEV1); > + break; > + default: > + set_feature (FEATURE_ACEV1); > + break; > + } > } > } > Thanks, Dipesh
