From: Pan Li <[email protected]>
Add test cases for the register group overlap of the widening
reduction vwredsum.vs, to ensure the scalar operand vs1 will not
fall inside the vs2 register group.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h:
Add new macros for the widening reduction test cases.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m8.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m8.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m8.c: New
test.
Signed-off-by: Pan Li <[email protected]>
---
.../rvv/autovec/group_overlap/group_overlap.h | 79 +++++++++++++++++++
.../group_overlap/vwredsum_vs-i16-m1.c | 20 +++++
.../group_overlap/vwredsum_vs-i16-m2.c | 23 ++++++
.../group_overlap/vwredsum_vs-i16-m4.c | 23 ++++++
.../group_overlap/vwredsum_vs-i16-m8.c | 23 ++++++
.../group_overlap/vwredsum_vs-i32-m1.c | 20 +++++
.../group_overlap/vwredsum_vs-i32-m2.c | 23 ++++++
.../group_overlap/vwredsum_vs-i32-m4.c | 23 ++++++
.../group_overlap/vwredsum_vs-i32-m8.c | 23 ++++++
.../autovec/group_overlap/vwredsum_vs-i8-m1.c | 20 +++++
.../autovec/group_overlap/vwredsum_vs-i8-m2.c | 23 ++++++
.../autovec/group_overlap/vwredsum_vs-i8-m4.c | 23 ++++++
.../autovec/group_overlap/vwredsum_vs-i8-m8.c | 23 ++++++
13 files changed, 346 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m8.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h
index 0eb77eb931b..8e3792adcf9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h
@@ -1240,6 +1240,54 @@
ST_F ((void *)out, vd0, VL); OUT += VL; \
ST_F ((void *)out, vd1, VL); OUT += VL; \
+/* A widening reduction reads vs1 with EEW = 2 * SEW while vs2 is read with
+ EEW = SEW, thus vs1 must not fall inside the vs2 register group. Taking vs1
+ out of the vs2 register group itself is the only way the two can be asked to
+ overlap: RI_F reinterprets the narrowed vector as the widened element type
+ and GET_F extracts its IDX-th LMUL1 piece, which lives in the vs2 register
+ group. */
+#define LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2(NT, WT, WNT, LD_NF, RI_F, GET_F, \
+ IDX, OUT_F, ST_F, OUT, START, VL) \
+ NT vs0 = LD_NF ((void *)START, VL); START += VL; \
+ NT vs1 = LD_NF ((void *)START, VL); START += VL; \
+ \
+ asm volatile("nop" ::: "memory"); \
+ \
+ WNT vr0 = RI_F (vs0); \
+ WNT vr1 = RI_F (vs1); \
+ \
+ WT vt0 = GET_F (vr0, IDX); \
+ WT vt1 = GET_F (vr1, IDX); \
+ \
+ WT vd0 = OUT_F (vs0, vt0, VL); \
+ WT vd1 = OUT_F (vs1, vt1, VL); \
+ \
+ asm volatile("nop" ::: "memory"); \
+ \
+ ST_F ((void *)out, vd0, VL); OUT += VL; \
+ ST_F ((void *)out, vd1, VL); OUT += VL; \
+
+/* Like LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2 but vs2 is a LMUL1 register group
+ already, thus reinterpreting it as the widened element type is enough to ask
+ for vs1 and vs2 to be the very same register. */
+#define LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2(NT, WT, LD_NF, RI_F, OUT_F, \
+ ST_F, OUT, START, VL) \
+ NT vs0 = LD_NF ((void *)START, VL); START += VL; \
+ NT vs1 = LD_NF ((void *)START, VL); START += VL; \
+ \
+ asm volatile("nop" ::: "memory"); \
+ \
+ WT vt0 = RI_F (vs0); \
+ WT vt1 = RI_F (vs1); \
+ \
+ WT vd0 = OUT_F (vs0, vt0, VL); \
+ WT vd1 = OUT_F (vs1, vt1, VL); \
+ \
+ asm volatile("nop" ::: "memory"); \
+ \
+ ST_F ((void *)out, vd0, VL); OUT += VL; \
+ ST_F ((void *)out, vd1, VL); OUT += VL; \
+
#define DEF_GROUP_OVERLAP_UNARY_0(VL_F, NT, WT, LD_F, OUT_F, ST_F, NAME, \
LOOP_BODY) \
void test_group_overlap_##NAME##_##NT##_unary_0(uint8_t *data, \
@@ -1433,4 +1481,35 @@
} \
}
+#define DEF_GROUP_OVERLAP_REDUCE_0(VL_F, NT, WT, WNT, LD_NF, RI_F, GET_F, \
+ IDX, OUT_F, ST_F, NAME, LOOP_BODY) \
+ void test_group_overlap_##NAME##_##NT##_reduce_0(uint8_t *data, \
+ uint8_t *out, \
+ size_t limit) \
+ { \
+ uint8_t *start = data; \
+ uint8_t *end = data + limit; \
+ size_t vl = VL_F (); \
+ \
+ while (start < end) { \
+ LOOP_BODY (NT, WT, WNT, LD_NF, RI_F, GET_F, IDX, OUT_F, ST_F, out, \
+ start, vl); \
+ } \
+ }
+
+#define DEF_GROUP_OVERLAP_REDUCE_1(VL_F, NT, WT, LD_NF, RI_F, OUT_F, ST_F, \
+ NAME, LOOP_BODY) \
+ void test_group_overlap_##NAME##_##NT##_reduce_1(uint8_t *data, \
+ uint8_t *out, \
+ size_t limit) \
+ { \
+ uint8_t *start = data; \
+ uint8_t *end = data + limit; \
+ size_t vl = VL_F (); \
+ \
+ while (start < end) { \
+ LOOP_BODY (NT, WT, LD_NF, RI_F, OUT_F, ST_F, out, start, vl); \
+ } \
+ }
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m1.c
new file mode 100644
index 00000000000..80a938b4300
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_1(
+ __riscv_vsetvlmax_e16m1,
+ vint16m1_t,
+ vint32m1_t,
+ __riscv_vle16_v_i16m1,
+ __riscv_vreinterpret_v_i16m1_i32m1,
+ __riscv_vwredsum_vs_i16m1_i32m1,
+ __riscv_vse32_v_i32m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v0,v2,v3([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v5,v1,v4([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vwredsum\.vs\s+v[0-9]+,v1,v1([^0-9]|$)} }
} */
+/* { dg-final { scan-assembler-not {vwredsum\.vs\s+v[0-9]+,v2,v2([^0-9]|$)} }
} */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m2.c
new file mode 100644
index 00000000000..874c04cce89
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e16m2,
+ vint16m2_t,
+ vint32m1_t,
+ vint32m2_t,
+ __riscv_vle16_v_i16m2,
+ __riscv_vreinterpret_v_i16m2_i32m2,
+ __riscv_vget_v_i32m2_i32m1,
+ 1,
+ __riscv_vwredsum_vs_i16m2_i32m1,
+ __riscv_vse32_v_i32m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v4,v4,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v2,v2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v2,v(2|3)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v4,v(4|5)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m4.c
new file mode 100644
index 00000000000..37c1bf81970
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e16m4,
+ vint16m4_t,
+ vint32m1_t,
+ vint32m4_t,
+ __riscv_vle16_v_i16m4,
+ __riscv_vreinterpret_v_i16m4_i32m4,
+ __riscv_vget_v_i32m4_i32m1,
+ 3,
+ __riscv_vwredsum_vs_i16m4_i32m1,
+ __riscv_vse32_v_i32m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v8,v8,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v4,v4,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v4,v(4|5|6|7)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v8,v(8|9|10|11)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m8.c
new file mode 100644
index 00000000000..fada697634b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i16-m8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e16m8,
+ vint16m8_t,
+ vint32m1_t,
+ vint32m8_t,
+ __riscv_vle16_v_i16m8,
+ __riscv_vreinterpret_v_i16m8_i32m8,
+ __riscv_vget_v_i32m8_i32m1,
+ 7,
+ __riscv_vwredsum_vs_i16m8_i32m1,
+ __riscv_vse32_v_i32m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v16,v16,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v8,v8,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v8,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v16,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m1.c
new file mode 100644
index 00000000000..b23dd7f37a8
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_1(
+ __riscv_vsetvlmax_e32m1,
+ vint32m1_t,
+ vint64m1_t,
+ __riscv_vle32_v_i32m1,
+ __riscv_vreinterpret_v_i32m1_i64m1,
+ __riscv_vwredsum_vs_i32m1_i64m1,
+ __riscv_vse64_v_i64m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v0,v2,v3([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v5,v1,v4([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vwredsum\.vs\s+v[0-9]+,v1,v1([^0-9]|$)} }
} */
+/* { dg-final { scan-assembler-not {vwredsum\.vs\s+v[0-9]+,v2,v2([^0-9]|$)} }
} */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m2.c
new file mode 100644
index 00000000000..1d431d68370
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e32m2,
+ vint32m2_t,
+ vint64m1_t,
+ vint64m2_t,
+ __riscv_vle32_v_i32m2,
+ __riscv_vreinterpret_v_i32m2_i64m2,
+ __riscv_vget_v_i64m2_i64m1,
+ 1,
+ __riscv_vwredsum_vs_i32m2_i64m1,
+ __riscv_vse64_v_i64m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v4,v4,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v2,v2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v2,v(2|3)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v4,v(4|5)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m4.c
new file mode 100644
index 00000000000..7a7e37e8784
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e32m4,
+ vint32m4_t,
+ vint64m1_t,
+ vint64m4_t,
+ __riscv_vle32_v_i32m4,
+ __riscv_vreinterpret_v_i32m4_i64m4,
+ __riscv_vget_v_i64m4_i64m1,
+ 3,
+ __riscv_vwredsum_vs_i32m4_i64m1,
+ __riscv_vse64_v_i64m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v8,v8,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v4,v4,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v4,v(4|5|6|7)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v8,v(8|9|10|11)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m8.c
new file mode 100644
index 00000000000..8c969122b9b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i32-m8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e32m8,
+ vint32m8_t,
+ vint64m1_t,
+ vint64m8_t,
+ __riscv_vle32_v_i32m8,
+ __riscv_vreinterpret_v_i32m8_i64m8,
+ __riscv_vget_v_i64m8_i64m1,
+ 7,
+ __riscv_vwredsum_vs_i32m8_i64m1,
+ __riscv_vse64_v_i64m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v16,v16,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v8,v8,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v8,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v16,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m1.c
new file mode 100644
index 00000000000..581f60d87da
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_1(
+ __riscv_vsetvlmax_e8m1,
+ vint8m1_t,
+ vint16m1_t,
+ __riscv_vle8_v_i8m1,
+ __riscv_vreinterpret_v_i8m1_i16m1,
+ __riscv_vwredsum_vs_i8m1_i16m1,
+ __riscv_vse16_v_i16m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v0,v2,v3([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v5,v1,v4([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not {vwredsum\.vs\s+v[0-9]+,v1,v1([^0-9]|$)} }
} */
+/* { dg-final { scan-assembler-not {vwredsum\.vs\s+v[0-9]+,v2,v2([^0-9]|$)} }
} */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m2.c
new file mode 100644
index 00000000000..204f6567d7b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e8m2,
+ vint8m2_t,
+ vint16m1_t,
+ vint16m2_t,
+ __riscv_vle8_v_i8m2,
+ __riscv_vreinterpret_v_i8m2_i16m2,
+ __riscv_vget_v_i16m2_i16m1,
+ 1,
+ __riscv_vwredsum_vs_i8m2_i16m1,
+ __riscv_vse16_v_i16m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v4,v4,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v2,v2,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v2,v(2|3)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v4,v(4|5)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m4.c
new file mode 100644
index 00000000000..107af1359bf
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e8m4,
+ vint8m4_t,
+ vint16m1_t,
+ vint16m4_t,
+ __riscv_vle8_v_i8m4,
+ __riscv_vreinterpret_v_i8m4_i16m4,
+ __riscv_vget_v_i16m4_i16m1,
+ 3,
+ __riscv_vwredsum_vs_i8m4_i16m1,
+ __riscv_vse16_v_i16m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v8,v8,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v4,v4,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v4,v(4|5|6|7)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v8,v(8|9|10|11)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m8.c
new file mode 100644
index 00000000000..c08e4ce1b03
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsum_vs-i8-m8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e8m8,
+ vint8m8_t,
+ vint16m1_t,
+ vint16m8_t,
+ __riscv_vle8_v_i8m8,
+ __riscv_vreinterpret_v_i8m8_i16m8,
+ __riscv_vget_v_i16m8_i16m1,
+ 7,
+ __riscv_vwredsum_vs_i8m8_i16m1,
+ __riscv_vse16_v_i16m1,
+ vwredsum_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v16,v16,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v8,v8,v0([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v8,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsum\.vs\s+v[0-9]+,v16,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */
--
2.43.0
