From: Pan Li <[email protected]>
Add test cases for the register group overlap of the widening
reduction vwredsumu.vs, to ensure the scalar operand vs1 will not
fall inside the vs2 register group.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m8.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m8.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m8.c: New
test.
Signed-off-by: Pan Li <[email protected]>
---
.../group_overlap/vwredsumu_vs-u16-m1.c | 20 ++++++++++++++++
.../group_overlap/vwredsumu_vs-u16-m2.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u16-m4.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u16-m8.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u32-m1.c | 20 ++++++++++++++++
.../group_overlap/vwredsumu_vs-u32-m2.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u32-m4.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u32-m8.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u8-m1.c | 20 ++++++++++++++++
.../group_overlap/vwredsumu_vs-u8-m2.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u8-m4.c | 23 +++++++++++++++++++
.../group_overlap/vwredsumu_vs-u8-m8.c | 23 +++++++++++++++++++
12 files changed, 267 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m8.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m1.c
new file mode 100644
index 00000000000..b77a079293e
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_1(
+ __riscv_vsetvlmax_e16m1,
+ vuint16m1_t,
+ vuint32m1_t,
+ __riscv_vle16_v_u16m1,
+ __riscv_vreinterpret_v_u16m1_u32m1,
+ __riscv_vwredsumu_vs_u16m1_u32m1,
+ __riscv_vse32_v_u32m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v0,v2,v3([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v5,v1,v4([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not {vwredsumu\.vs\s+v[0-9]+,v1,v1([^0-9]|$)} }
} */
+/* { dg-final { scan-assembler-not {vwredsumu\.vs\s+v[0-9]+,v2,v2([^0-9]|$)} }
} */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m2.c
new file mode 100644
index 00000000000..338216a1219
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e16m2,
+ vuint16m2_t,
+ vuint32m1_t,
+ vuint32m2_t,
+ __riscv_vle16_v_u16m2,
+ __riscv_vreinterpret_v_u16m2_u32m2,
+ __riscv_vget_v_u32m2_u32m1,
+ 1,
+ __riscv_vwredsumu_vs_u16m2_u32m1,
+ __riscv_vse32_v_u32m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v4,v4,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v2,v2,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v2,v(2|3)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v4,v(4|5)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m4.c
new file mode 100644
index 00000000000..7751133654e
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e16m4,
+ vuint16m4_t,
+ vuint32m1_t,
+ vuint32m4_t,
+ __riscv_vle16_v_u16m4,
+ __riscv_vreinterpret_v_u16m4_u32m4,
+ __riscv_vget_v_u32m4_u32m1,
+ 3,
+ __riscv_vwredsumu_vs_u16m4_u32m1,
+ __riscv_vse32_v_u32m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v8,v8,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v4,v4,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v4,v(4|5|6|7)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v8,v(8|9|10|11)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m8.c
new file mode 100644
index 00000000000..447692000fa
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u16-m8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e16m8,
+ vuint16m8_t,
+ vuint32m1_t,
+ vuint32m8_t,
+ __riscv_vle16_v_u16m8,
+ __riscv_vreinterpret_v_u16m8_u32m8,
+ __riscv_vget_v_u32m8_u32m1,
+ 7,
+ __riscv_vwredsumu_vs_u16m8_u32m1,
+ __riscv_vse32_v_u32m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v16,v16,v1([^0-9]|$)} 1
} } */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v8,v8,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v8,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v16,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m1.c
new file mode 100644
index 00000000000..a5c66089241
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_1(
+ __riscv_vsetvlmax_e32m1,
+ vuint32m1_t,
+ vuint64m1_t,
+ __riscv_vle32_v_u32m1,
+ __riscv_vreinterpret_v_u32m1_u64m1,
+ __riscv_vwredsumu_vs_u32m1_u64m1,
+ __riscv_vse64_v_u64m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v0,v2,v3([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v5,v1,v4([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not {vwredsumu\.vs\s+v[0-9]+,v1,v1([^0-9]|$)} }
} */
+/* { dg-final { scan-assembler-not {vwredsumu\.vs\s+v[0-9]+,v2,v2([^0-9]|$)} }
} */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m2.c
new file mode 100644
index 00000000000..056a2ddb27d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e32m2,
+ vuint32m2_t,
+ vuint64m1_t,
+ vuint64m2_t,
+ __riscv_vle32_v_u32m2,
+ __riscv_vreinterpret_v_u32m2_u64m2,
+ __riscv_vget_v_u64m2_u64m1,
+ 1,
+ __riscv_vwredsumu_vs_u32m2_u64m1,
+ __riscv_vse64_v_u64m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v4,v4,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v2,v2,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v2,v(2|3)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v4,v(4|5)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m4.c
new file mode 100644
index 00000000000..733d96bd40f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e32m4,
+ vuint32m4_t,
+ vuint64m1_t,
+ vuint64m4_t,
+ __riscv_vle32_v_u32m4,
+ __riscv_vreinterpret_v_u32m4_u64m4,
+ __riscv_vget_v_u64m4_u64m1,
+ 3,
+ __riscv_vwredsumu_vs_u32m4_u64m1,
+ __riscv_vse64_v_u64m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v8,v8,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v4,v4,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v4,v(4|5|6|7)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v8,v(8|9|10|11)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m8.c
new file mode 100644
index 00000000000..a5445c04033
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u32-m8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e32m8,
+ vuint32m8_t,
+ vuint64m1_t,
+ vuint64m8_t,
+ __riscv_vle32_v_u32m8,
+ __riscv_vreinterpret_v_u32m8_u64m8,
+ __riscv_vget_v_u64m8_u64m1,
+ 7,
+ __riscv_vwredsumu_vs_u32m8_u64m1,
+ __riscv_vse64_v_u64m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v16,v16,v1([^0-9]|$)} 1
} } */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v8,v8,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v8,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v16,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m1.c
new file mode 100644
index 00000000000..8b98931f32c
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_1(
+ __riscv_vsetvlmax_e8m1,
+ vuint8m1_t,
+ vuint16m1_t,
+ __riscv_vle8_v_u8m1,
+ __riscv_vreinterpret_v_u8m1_u16m1,
+ __riscv_vwredsumu_vs_u8m1_u16m1,
+ __riscv_vse16_v_u16m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_LMUL1_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v0,v2,v3([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v5,v1,v4([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not {vwredsumu\.vs\s+v[0-9]+,v1,v1([^0-9]|$)} }
} */
+/* { dg-final { scan-assembler-not {vwredsumu\.vs\s+v[0-9]+,v2,v2([^0-9]|$)} }
} */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m2.c
new file mode 100644
index 00000000000..665e9e7d535
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e8m2,
+ vuint8m2_t,
+ vuint16m1_t,
+ vuint16m2_t,
+ __riscv_vle8_v_u8m2,
+ __riscv_vreinterpret_v_u8m2_u16m2,
+ __riscv_vget_v_u16m2_u16m1,
+ 1,
+ __riscv_vwredsumu_vs_u8m2_u16m1,
+ __riscv_vse16_v_u16m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v4,v4,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v2,v2,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v2,v(2|3)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v4,v(4|5)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m4.c
new file mode 100644
index 00000000000..2b79c970e45
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e8m4,
+ vuint8m4_t,
+ vuint16m1_t,
+ vuint16m4_t,
+ __riscv_vle8_v_u8m4,
+ __riscv_vreinterpret_v_u8m4_u16m4,
+ __riscv_vget_v_u16m4_u16m1,
+ 3,
+ __riscv_vwredsumu_vs_u8m4_u16m1,
+ __riscv_vse16_v_u16m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v8,v8,v1([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v4,v4,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v4,v(4|5|6|7)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v8,v(8|9|10|11)([^0-9]|$)} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m8.c
new file mode 100644
index 00000000000..87a8b619ed6
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwredsumu_vs-u8-m8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_REDUCE_0(
+ __riscv_vsetvlmax_e8m8,
+ vuint8m8_t,
+ vuint16m1_t,
+ vuint16m8_t,
+ __riscv_vle8_v_u8m8,
+ __riscv_vreinterpret_v_u8m8_u16m8,
+ __riscv_vget_v_u16m8_u16m1,
+ 7,
+ __riscv_vwredsumu_vs_u8m8_u16m1,
+ __riscv_vse16_v_u16m1,
+ vwredsumu_vs,
+ LOOP_WIDEN_REDUCE_BODY_OVERLAP_X2)
+
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v16,v16,v1([^0-9]|$)} 1
} } */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v8,v8,v0([^0-9]|$)} 1 }
} */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v8,v(8|9|10|11|12|13|14|15)([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not
{vwredsumu\.vs\s+v[0-9]+,v16,v(16|17|18|19|20|21|22|23)([^0-9]|$)} } } */
--
2.43.0
