When the iteration count is unknown, actually compare the costs of
different VLA modes instead of blindly choosing the bigger LMUL as long
as there's no unexpected spill. This can prevent some cases when
-mrvv-max-lmul=dynamic emits worse code than -mrvv-max-lmul=m8, and
consistent with the current implementation of
check_vectorise_memory_operation in riscv-string.cc, which chooses the
smallest possible LMUL, instead of m8 for all cases.
This patch used to be a part of the m1-dynamic patch I proposed earlier,
but as this can be justified independently, I split this out.
As I changed the `else if` branch to an independent if-clause, it can
now affect both dynamic and conv-dynamic. I am not quite sure but I
guess avoiding a VLS loop for unknown niter cases would be reasonable as
well for conv-dynamic when neither is preferred by the conv-dynamic
heuristics.
When running the regression tests, I found several testcases, including
vec_sat_u_sub_zip.c, contain multiline DejaGnu directives that are not
supported by the DejaGnu framework. I plan to fix them in a separate
testsuite-only patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p):
Compare VLA costs under -mrvv-max-lmul=dynamic.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Update
expectation.
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto.
* gcc.dg/vect/costmodel/riscv/rvv/pr111848.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto.
---
gcc/config/riscv/riscv-vector-costs.cc | 12 ++----------
.../vect/costmodel/riscv/rvv/dynamic-lmul4-6.c | 4 ++--
.../vect/costmodel/riscv/rvv/dynamic-lmul8-12.c | 4 ++--
.../gcc.dg/vect/costmodel/riscv/rvv/pr111848.c | 2 +-
.../gcc.target/riscv/rvv/autovec/partial/slp-16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c | 2 +-
6 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-costs.cc
b/gcc/config/riscv/riscv-vector-costs.cc
index dfb80bee679..73e73634503 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -1261,14 +1261,6 @@ costs::better_main_loop_than_p (const vector_costs
*uncast_other) const
return false;
}
}
- else
- {
- if (dump_enabled_p ())
- dump_printf_loc (MSG_NOTE, vect_location,
- "Keep current LMUL loop because"
- " it is unknown NITERS\n");
- return false;
- }
}
}
/* If NITERS is unknown, we should not use VLS modes to vectorize
@@ -1277,8 +1269,8 @@ costs::better_main_loop_than_p (const vector_costs
*uncast_other) const
and partial vectors (VLAmodes) on loop epilogue which is very
inefficient. Instead, we should apply partial vectors (VLAmodes)
on loop body without an epilogue on unknown NITERS loop. */
- else if (!LOOP_VINFO_NITERS_KNOWN_P (this_loop_vinfo)
- && m_cost_type == VLS_VECTOR_COST)
+ if (!LOOP_VINFO_NITERS_KNOWN_P (this_loop_vinfo)
+ && m_cost_type == VLS_VECTOR_COST)
return false;
/* Fall back to generic costing if either iteration count is unknown. For
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index 365fdf2a749..ba2eacaccd2 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -20,8 +20,8 @@ foo (uint8_t *restrict a, uint8_t *restrict b, int n)
}
}
-/* { dg-final { scan-assembler {e8,m4} } } */
-/* { dg-final { scan-assembler-times {csrr} 1 } } */
+/* { dg-final { scan-assembler {e8,m1} } } */
+/* { dg-final { scan-assembler-times {csrr} 0 } } */
/* Since we don't support VLA SLP for LMUL = 8, dynamic LMUL cost model start
from LMUL = 4. */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it
has unexpected spills" "vect" } } */
/* { dg-final { scan-tree-dump-not "Maximum lmul = 8" "vect" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
index c55546394de..0f75505f1de 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
@@ -17,8 +17,8 @@ foo (int *restrict a, int *restrict b, int n)
}
}
-/* { dg-final { scan-assembler {e32,m8} } } */
-/* { dg-final { scan-assembler-times {csrr} 1 } } */
+/* { dg-final { scan-assembler {e32,m1} } } */
+/* { dg-final { scan-assembler-times {csrr} 0 } } */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it
has unexpected spills" "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" { xfail *-*-*
} } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 2" 1 "vect" { xfail *-*-*
} } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
index 339c80f8805..2801ef49925 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
@@ -28,7 +28,7 @@ f3 (uint8_t *restrict a, uint8_t *restrict b,
}
}
-/* { dg-final { scan-assembler {e8,m4} } } */
+/* { dg-final { scan-assembler {e8,m1} } } */
/* { dg-final { scan-assembler-not {jr} } } */
/* { dg-final { scan-assembler-times {ret} 1 } } */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it
has unexpected spills" "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index b31453852b2..bf1bed97551 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -20,6 +20,6 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
}
/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are
chosen instead of SLP. */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail {
any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" "-mrvv-max-lmul=m4"
"-mrvv-max-lmul=m8" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts
"-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8"
} } } } */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail *-*-*
} } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail *-*-* } } } */
/* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
index 5988df689d0..2a632838d30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
@@ -17,4 +17,4 @@ DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 { target { any-ops
"-mrvv-vector-bits=zvl"
} } } } */
-/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
+/* { dg-final { scan-assembler {vnclipu\.wi} } } */
--
2.47.1
