> We tried a PoC implementation of the M1-epilogue scheme (M8/M4 > length-controlled > main loop + M1 length-controlled epilogue), but it turned out that most SPEC > CPU > 2017 cases did not show any performance improvement on our internal uarch, > some > even regressing, showing that the performance impact of length checks can be > huge.
Was this with --param=partial-vector-usage=1 or something else? I'd really like to see an example of a loop where this is worse than e.g. an LMUL4 loop with small VL. Maybe that would help us steer the implementation and codegen. -- Regards Robin
