On Thu, Sep 10, 2026 at 4:25 PM Stefan Schulze Frielinghaus
<[email protected]> wrote:
>
> From: Stefan Schulze Frielinghaus <[email protected]>
>
> Initially asm-hard-reg-2.c was intended to be considered only on 64-bit
> x86. Commit r16-3110 restricted this to { ! ia32 } which still includes
> the test for i?86 ILP32 for which we get "warning: unsupported size for
I couldn't reproduce this. I got
UNSUPPORTED: gcc.dg/asm-hard-reg-2.c
for Linux/i686. How did you test for Linux/i686?
> integer register". Since the test is about integer type long long
> and GPRs, restrict this to lp64.
>
> Test asm-hard-reg-5.c fails on powerpc64-*-* since option -maltivec is
> missing.
>
> Test asm-hard-reg-6.c is failing for ARM Thumb-2 e.g. if options -mthumb
> -march=armv8.1-m.main+mve.fp+fp.dp -mtune=cortex-m55 -mfloat-abi=hard
> -mfpu=auto are used. In that case GPR pairs must be in even/odd pairs in
> contrast to Thumb-1. Fix this by changing GPR3 to r4.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/asm-hard-reg-2.c: Restrict to x86 && lp64.
> * gcc.dg/asm-hard-reg-5.c: Ensure option -maltivec is specified
> for powerpc64-*-*. For x86, copy the target selector from
> dg-compile for the scan-assembler directive.
> * gcc.dg/asm-hard-reg-6.c: Use an even/odd register pair for ARM
> Thumb-2.
> ---
> Tested via cross compilers for
> - arm-unknown-linux-gnueabi
> - i686-ubuntu16.04-linux-gnu
> - powerpc64le-unknown-linux-gnu
> - powerpc64-unknown-linux-gnu
> - powerpc-unknown-linux-gnu
> - x86_64-unknown-linux-gnu
>
> I guess this commit falls under the "obvious rule", though, I will give
> maintainers some time to chime in before pushing this sometime next
> week.
>
> I hope to get a clean asm-hard-reg-*.c test suite some time. Sorry for
> all the noise; there are quite some configurations which were new to me.
>
> gcc/testsuite/gcc.dg/asm-hard-reg-2.c | 4 ++--
> gcc/testsuite/gcc.dg/asm-hard-reg-5.c | 5 +++--
> gcc/testsuite/gcc.dg/asm-hard-reg-6.c | 4 ++--
> 3 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> b/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> index 5a60f9be4f2..12b4a601984 100644
> --- a/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> @@ -1,4 +1,4 @@
> -/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
> s390*-*-* } || { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } } */
> +/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
> s390*-*-* } || { x86 && lp64 } } } } */
> /* { dg-options "-std=c99" } we need long long */
>
> #if defined (__aarch64__)
> @@ -15,7 +15,7 @@
> /* { dg-final { scan-assembler-times "foo\t%r4" 2 { target { s390*-*-* } } }
> } */
> #elif defined (__x86_64__)
> # define GPR "{rcx}"
> -/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { i?86-*-*
> x86_64-*-* } } } } */
> +/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { x86 && lp64 }
> } } } */
> #endif
>
> long long
> diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> index ea7907ae2a0..38486487c24 100644
> --- a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> @@ -1,4 +1,4 @@
> -/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
> s390*-*-* } || { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } } */
> +/* { dg-do compile { target { { aarch64*-*-* riscv64-*-* s390*-*-* } || { {
> powerpc64*-*-* && powerpc_altivec_ok } || { x86_64-*-* && { ! ia32 } } } } }
> } */
>
> typedef int V __attribute__ ((vector_size (4 * sizeof (int))));
>
> @@ -7,6 +7,7 @@ typedef int V __attribute__ ((vector_size (4 * sizeof
> (int))));
> /* { dg-final { scan-assembler-times "foo\tv20" 2 { target { aarch64*-*-* }
> } } } */
> #elif defined (__powerpc__) || defined (__POWERPC__)
> # define VR "{v5}"
> +/* { dg-additional-options "-maltivec" { target { powerpc64*-*-* } } } */
> /* { dg-final { scan-assembler-times "foo\t5" 2 { target { powerpc64*-*-* }
> } } } */
> #elif defined (__riscv)
> # define VR "{v5}"
> @@ -18,7 +19,7 @@ typedef int V __attribute__ ((vector_size (4 * sizeof
> (int))));
> /* { dg-final { scan-assembler-times "foo\t%v5" 2 { target s390*-*-* } } } */
> #elif defined (__x86_64__)
> # define VR "{xmm9}"
> -/* { dg-final { scan-assembler-times "foo\t%xmm9" 2 { target { x86_64-*-* }
> } } } */
> +/* { dg-final { scan-assembler-times "foo\t%xmm9" 2 { target { x86_64-*-* &&
> { ! ia32 } } } } } */
> #endif
>
> V
> diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> index 37d15a6ed5c..5c1f8371897 100644
> --- a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> @@ -12,8 +12,8 @@
> #elif defined (__arm__)
> # define GPR1 "{r1}"
> # define GPR2 "{r2}"
> -# define GPR3 "{r3}"
> -/* { dg-final { scan-assembler-times "foo\tr1,r3" 1 { target { arm*-*-* } }
> } } */
> +# define GPR3 "{r4}"
> +/* { dg-final { scan-assembler-times "foo\tr1,r4" 1 { target { arm*-*-* } }
> } } */
> /* { dg-final { scan-assembler-times "bar\tr2,\\\[r1\\\]" 1 { target {
> arm*-*-* } } } } */
> #elif defined (__i386__)
> # define GPR1 "{eax}"
> --
> 2.54.0
>
--
H.J.
