On Thu, Sep 10, 2026 at 5:28 PM Stefan Schulze Frielinghaus
<[email protected]> wrote:
>
> On Thu, Sep 10, 2026 at 05:00:03PM +0800, H.J. Lu wrote:
> > On Thu, Sep 10, 2026 at 4:25 PM Stefan Schulze Frielinghaus
> > <[email protected]> wrote:
> > >
> > > From: Stefan Schulze Frielinghaus <[email protected]>
> > >
> > > Initially asm-hard-reg-2.c was intended to be considered only on 64-bit
> > > x86. Commit r16-3110 restricted this to { ! ia32 } which still includes
> > > the test for i?86 ILP32 for which we get "warning: unsupported size for
> >
> > I couldn't reproduce this. I got
> >
> > UNSUPPORTED: gcc.dg/asm-hard-reg-2.c
> >
> > for Linux/i686. How did you test for Linux/i686?
>
> My typical workflow is to use crosstool-ng in order to come up with a
> sysroot for my cross. I used configuration i686-ubuntu16.04-linux-gnu
> from crosstool-ng in order to build gcc with
> --target=i686-ubuntu16.04-linux-gnu --with-build-sysroot=$SYSROOT_DIR
>
> $ make check-gcc RUNTESTFLAGS="dg.exp=asm-hard-reg-2.c"
> ...
> FAIL: gcc.dg/asm-hard-reg-2.c (test for excess errors)
>
> Log file contains:
> Target is i686-ubuntu16.04-linux-gnu
> ...
> FAIL: gcc.dg/asm-hard-reg-2.c (test for excess errors)
> Excess errors:
> /devel/gcc/src/gcc/testsuite/gcc.dg/asm-hard-reg-2.c:24:27: error: expected
> '(' before 'GPR'
> /devel/gcc/src/gcc/testsuite/gcc.dg/asm-hard-reg-2.c:31:27: error: expected
> '(' before 'GPR'
>
> So the test is still run for me. If #define GPR is moved outside of the
> if x86_64, then I get
>
> FAIL: gcc.dg/asm-hard-reg-2.c (test for excess errors)
> Excess errors:
> /devel/gcc/src/gcc/testsuite/gcc.dg/asm-hard-reg-2.c:27:1: warning:
> unsupported size for integer register
> /devel/gcc/src/gcc/testsuite/gcc.dg/asm-hard-reg-2.c:34:1: warning:
> unsupported size for integer register
>
> Maybe my cross setup is broken then?
I have
[hjl@gnu-zen4-1 gcc]$ cat x.c
int dummy[sizeof (int) == 4 && sizeof (void *) == 4 && sizeof (long)
== 4 ? 1 : -1] = { __i386__ };
[hjl@gnu-zen4-1 gcc]$ ./xgcc -B./ -S x.c
[hjl@gnu-zen4-1 gcc]$ ./xgcc -v
Using built-in specs.
COLLECT_GCC=./xgcc
Target: i686-linux
Configured with: /export/gnu/import/git/sources/gcc/configure
--disable-bootstrap --enable-cet --with-demangler-in-ld i686-linux
--prefix=/usr/gcc-17.0.0-32bit --with-local-prefix=/usr/local
--enable-gnu-indirect-function --enable-clocale=gnu --with-system-zlib
--with-target-system-zlib --with-fpmath=sse --with-tls=gnu2
--disable-libcc1 --disable-libcilkrts --disable-libsanitizer
--enable-languages=c,c++,fortran,lto,objc,ada,obj-c++,go
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 17.0.0 20260910 (experimental) (GCC)
[hjl@gnu-zen4-1 gcc]$ gcc -S x.c
x.c:1:5: error: size of array ‘dummy’ is negative
1 | int dummy[sizeof (int) == 4 && sizeof (void *) == 4 && sizeof
(long) == 4 ? 1 : -1] = { __i386__ };
| ^~~~~
x.c:1:89: error: ‘__i386__’ undeclared here (not in a function)
1 | && sizeof (void *) == 4 && sizeof (long) == 4 ? 1 : -1] = { __i386__ };
| ^~~~~~~~
[hjl@gnu-zen4-1 gcc]$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/libexec/gcc/x86_64-redhat-linux/16/lto-wrapper
OFFLOAD_TARGET_NAMES=nvptx-none:amdgcn-amdhsa
OFFLOAD_TARGET_DEFAULT=1
Target: x86_64-redhat-linux
Configured with: ../configure --enable-bootstrap
--enable-languages=c,c++,fortran,objc,obj-c++,ada,go,d,m2,cobol,algol68,lto
--prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info
--with-bugurl=https://bugzilla.redhat.com/ --enable-shared
--enable-threads=posix --enable-checking=release --enable-multilib
--with-system-zlib --enable-__cxa_atexit
--disable-libunwind-exceptions --enable-gnu-unique-object
--enable-linker-build-id --with-gcc-major-version-only
--enable-libstdcxx-backtrace
--with-libstdcxx-zoneinfo=/usr/share/zoneinfo
--with-linker-hash-style=gnu --enable-plugin --enable-initfini-array
--with-isl=/builddir/build/BUILD/gcc-16.2.1-build/gcc-16.2.1-20260819/obj-x86_64-redhat-linux/isl-install
--enable-offload-targets=nvptx-none,amdgcn-amdhsa
--enable-offload-defaulted --without-cuda-driver
--enable-gnu-indirect-function --enable-cet --with-tune=generic
--with-tls=gnu2 --with-arch_32=i686 --with-multilib-list=m32,m64,mx32
--build=x86_64-redhat-linux --with-build-config=bootstrap-lto
--enable-link-serialization=1 --disable-libssp
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 16.2.1 20260819 (Red Hat 16.2.1-2) (GCC)
[hjl@gnu-zen4-1 gcc]$
What does
./xgcc -B./ -S x.c
report with your i686 gcc?
> Cheers,
> Stefan
>
> >
> > > integer register". Since the test is about integer type long long
> > > and GPRs, restrict this to lp64.
> > >
> > > Test asm-hard-reg-5.c fails on powerpc64-*-* since option -maltivec is
> > > missing.
> > >
> > > Test asm-hard-reg-6.c is failing for ARM Thumb-2 e.g. if options -mthumb
> > > -march=armv8.1-m.main+mve.fp+fp.dp -mtune=cortex-m55 -mfloat-abi=hard
> > > -mfpu=auto are used. In that case GPR pairs must be in even/odd pairs in
> > > contrast to Thumb-1. Fix this by changing GPR3 to r4.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.dg/asm-hard-reg-2.c: Restrict to x86 && lp64.
> > > * gcc.dg/asm-hard-reg-5.c: Ensure option -maltivec is specified
> > > for powerpc64-*-*. For x86, copy the target selector from
> > > dg-compile for the scan-assembler directive.
> > > * gcc.dg/asm-hard-reg-6.c: Use an even/odd register pair for ARM
> > > Thumb-2.
> > > ---
> > > Tested via cross compilers for
> > > - arm-unknown-linux-gnueabi
> > > - i686-ubuntu16.04-linux-gnu
> > > - powerpc64le-unknown-linux-gnu
> > > - powerpc64-unknown-linux-gnu
> > > - powerpc-unknown-linux-gnu
> > > - x86_64-unknown-linux-gnu
> > >
> > > I guess this commit falls under the "obvious rule", though, I will give
> > > maintainers some time to chime in before pushing this sometime next
> > > week.
> > >
> > > I hope to get a clean asm-hard-reg-*.c test suite some time. Sorry for
> > > all the noise; there are quite some configurations which were new to me.
> > >
> > > gcc/testsuite/gcc.dg/asm-hard-reg-2.c | 4 ++--
> > > gcc/testsuite/gcc.dg/asm-hard-reg-5.c | 5 +++--
> > > gcc/testsuite/gcc.dg/asm-hard-reg-6.c | 4 ++--
> > > 3 files changed, 7 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> > > b/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> > > index 5a60f9be4f2..12b4a601984 100644
> > > --- a/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> > > +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-2.c
> > > @@ -1,4 +1,4 @@
> > > -/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
> > > s390*-*-* } || { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } } */
> > > +/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
> > > s390*-*-* } || { x86 && lp64 } } } } */
> > > /* { dg-options "-std=c99" } we need long long */
> > >
> > > #if defined (__aarch64__)
> > > @@ -15,7 +15,7 @@
> > > /* { dg-final { scan-assembler-times "foo\t%r4" 2 { target { s390*-*-* }
> > > } } } */
> > > #elif defined (__x86_64__)
> > > # define GPR "{rcx}"
> > > -/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { i?86-*-*
> > > x86_64-*-* } } } } */
> > > +/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { x86 &&
> > > lp64 } } } } */
> > > #endif
> > >
> > > long long
> > > diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> > > b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> > > index ea7907ae2a0..38486487c24 100644
> > > --- a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> > > +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
> > > @@ -1,4 +1,4 @@
> > > -/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
> > > s390*-*-* } || { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } } */
> > > +/* { dg-do compile { target { { aarch64*-*-* riscv64-*-* s390*-*-* } ||
> > > { { powerpc64*-*-* && powerpc_altivec_ok } || { x86_64-*-* && { ! ia32 }
> > > } } } } } */
> > >
> > > typedef int V __attribute__ ((vector_size (4 * sizeof (int))));
> > >
> > > @@ -7,6 +7,7 @@ typedef int V __attribute__ ((vector_size (4 * sizeof
> > > (int))));
> > > /* { dg-final { scan-assembler-times "foo\tv20" 2 { target {
> > > aarch64*-*-* } } } } */
> > > #elif defined (__powerpc__) || defined (__POWERPC__)
> > > # define VR "{v5}"
> > > +/* { dg-additional-options "-maltivec" { target { powerpc64*-*-* } } } */
> > > /* { dg-final { scan-assembler-times "foo\t5" 2 { target {
> > > powerpc64*-*-* } } } } */
> > > #elif defined (__riscv)
> > > # define VR "{v5}"
> > > @@ -18,7 +19,7 @@ typedef int V __attribute__ ((vector_size (4 * sizeof
> > > (int))));
> > > /* { dg-final { scan-assembler-times "foo\t%v5" 2 { target s390*-*-* } }
> > > } */
> > > #elif defined (__x86_64__)
> > > # define VR "{xmm9}"
> > > -/* { dg-final { scan-assembler-times "foo\t%xmm9" 2 { target {
> > > x86_64-*-* } } } } */
> > > +/* { dg-final { scan-assembler-times "foo\t%xmm9" 2 { target {
> > > x86_64-*-* && { ! ia32 } } } } } */
> > > #endif
> > >
> > > V
> > > diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> > > b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> > > index 37d15a6ed5c..5c1f8371897 100644
> > > --- a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> > > +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
> > > @@ -12,8 +12,8 @@
> > > #elif defined (__arm__)
> > > # define GPR1 "{r1}"
> > > # define GPR2 "{r2}"
> > > -# define GPR3 "{r3}"
> > > -/* { dg-final { scan-assembler-times "foo\tr1,r3" 1 { target { arm*-*-*
> > > } } } } */
> > > +# define GPR3 "{r4}"
> > > +/* { dg-final { scan-assembler-times "foo\tr1,r4" 1 { target { arm*-*-*
> > > } } } } */
> > > /* { dg-final { scan-assembler-times "bar\tr2,\\\[r1\\\]" 1 { target {
> > > arm*-*-* } } } } */
> > > #elif defined (__i386__)
> > > # define GPR1 "{eax}"
> > > --
> > > 2.54.0
> > >
> >
> >
> > --
> > H.J.
--
H.J.
