From: Stefan Schulze Frielinghaus <[email protected]>

Test gcc.dg/asm-hard-reg-5.c might fail on powerpc64 with:

gcc.dg/asm-hard-reg-5.c:27:3: error: register 5 for operand 0 isn't suitable 
for data type
gcc.dg/asm-hard-reg-5.c:34:3: error: register 5 for operand 0 isn't suitable 
for data type

For powerpc64le there exists no CPU without altivec support which is why
-maltivec is implied.  For powerpc64 this does not hold which is why for
this test -maltivec must be specified, or the other way around must be
skipped if there is no altivec support.

I'm not entirely sure whether I grasped all the nitty gritty details of
rs6000_target_modify_macros and whether I should use target selector
powerpc_vsx or as done by this patch powerpc_altivec_ok.  Any comments?

Tested on cfarm121 where we have, now:
PASS: gcc.dg/asm-hard-reg-5.c (test for excess errors)
PASS: gcc.dg/asm-hard-reg-5.c scan-assembler-times foo\t5 2

---
 gcc/testsuite/gcc.dg/asm-hard-reg-5.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c 
b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
index ea7907ae2a0..12c442f9777 100644
--- a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
+++ b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-* 
s390*-*-* } || { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } } */
+/* { dg-do compile { target { { aarch64*-*-* riscv64-*-* s390*-*-* } || { { 
powerpc64*-*-* && powerpc_altivec_ok } || { x86_64-*-* && { ! ia32 } } } } } } 
*/
 
 typedef int V __attribute__ ((vector_size (4 * sizeof (int))));
 
@@ -7,6 +7,7 @@ typedef int V __attribute__ ((vector_size (4 * sizeof (int))));
 /* { dg-final { scan-assembler-times "foo\tv20" 2 { target { aarch64*-*-* } } 
} } */
 #elif defined (__powerpc__) || defined (__POWERPC__)
 # define VR "{v5}"
+/* { dg-additional-options "-maltivec" { target { powerpc64*-*-* && 
powerpc_altivec_ok } } } */
 /* { dg-final { scan-assembler-times "foo\t5" 2 { target { powerpc64*-*-* } } 
} } */
 #elif defined (__riscv)
 # define VR "{v5}"
-- 
2.55.0

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