On Thu, Sep 10, 2026 at 05:53:22PM +0200, Stefan Schulze Frielinghaus wrote: > From: Stefan Schulze Frielinghaus <[email protected]> > > Test gcc.dg/asm-hard-reg-5.c might fail on powerpc64 with: > > gcc.dg/asm-hard-reg-5.c:27:3: error: register 5 for operand 0 isn't suitable > for data type > gcc.dg/asm-hard-reg-5.c:34:3: error: register 5 for operand 0 isn't suitable > for data type > > For powerpc64le there exists no CPU without altivec support which is why > -maltivec is implied. For powerpc64 this does not hold which is why for > this test -maltivec must be specified, or the other way around must be > skipped if there is no altivec support. > > I'm not entirely sure whether I grasped all the nitty gritty details of > rs6000_target_modify_macros and whether I should use target selector > powerpc_vsx or as done by this patch powerpc_altivec_ok. Any comments? > > Tested on cfarm121 where we have, now: > PASS: gcc.dg/asm-hard-reg-5.c (test for excess errors) > PASS: gcc.dg/asm-hard-reg-5.c scan-assembler-times foo\t5 2 > > --- > gcc/testsuite/gcc.dg/asm-hard-reg-5.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-)
This is ok for the master branch. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
