[PATCH 2/2] arm: write the signed high-part multiply with smul_highpart

[Dominic P]

Use smul_highpart in smmulsi3 and *smmlasi4, as Roger Sayle suggested.
Code is unchanged apart from the scratch registers in div_seven, which
the test now accepts in either order.

Bootstrapped on x86_64-pc-linux-gnu, regression tested on arm-none-eabi.

Assisted-by: Claude Opus 5 (Anthropic)

gcc/ChangeLog:

        * config/arm/arm.md (smmulsi3, *smmlasi4): Use smul_highpart.

gcc/testsuite/ChangeLog:

        * gcc.target/arm/smmul-1.c (div_seven): Accept either scratch
        register.

Signed-off-by: Dominic P <g...@gcc.dp11.uk>
---
 gcc/config/arm/arm.md                  | 16 ++++------------
 gcc/testsuite/gcc.target/arm/smmul-1.c |  8 ++++----
 2 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 56395699efe..dd8c015e43d 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2500,12 +2500,8 @@
 
 (define_insn "smmulsi3"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-       (truncate:SI
-        (lshiftrt:DI
-         (mult:DI
-          (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
-          (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
-         (const_int 32))))]
+       (smul_highpart:SI (match_operand:SI 1 "s_register_operand" "%r")
+                         (match_operand:SI 2 "s_register_operand" "r")))]
   "TARGET_INT_SIMD"
   "smmul%?\\t%0, %1, %2"
   [(set_attr "type" "smmul")
@@ -2515,12 +2511,8 @@
 (define_insn "*smmlasi4"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
        (plus:SI
-        (truncate:SI
-         (lshiftrt:DI
-          (mult:DI
-           (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
-           (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
-          (const_int 32)))
+        (smul_highpart:SI (match_operand:SI 1 "s_register_operand" "%r")
+                          (match_operand:SI 2 "s_register_operand" "r"))
         (match_operand:SI 3 "s_register_operand" "r")))]
   "TARGET_INT_SIMD"
   "smmla%?\\t%0, %1, %2, %3"
diff --git a/gcc/testsuite/gcc.target/arm/smmul-1.c 
b/gcc/testsuite/gcc.target/arm/smmul-1.c
index 90b0d20adf7..93c31987a2c 100644
--- a/gcc/testsuite/gcc.target/arm/smmul-1.c
+++ b/gcc/testsuite/gcc.target/arm/smmul-1.c
@@ -51,10 +51,10 @@ mul_high_sub (int a, int b, int c)
 
 /*
 **div_seven:
-**     ldr     r3, \.L[0-9]+
-**     asr     r2, r0, #31
-**     smmla   r0, r0, r3, r0
-**     rsb     r0, r2, r0, asr #2
+**     ldr     (r[0-9]+), \.L[0-9]+
+**     asr     (r[0-9]+), r0, #31
+**     smmla   r0, r0, \1, r0
+**     rsb     r0, \2, r0, asr #2
 **     bx      lr
 */
 int
-- 
2.55.0