> Like vfw{add,sub,mul}.vv, allow the rvv register overlap for the
> dual widen float vf insns, aka vfwadd.vf, vfwsub.vf and vfwmul.vf.LGTM, thanks. -- Regards Robin
- [PATCH v1 0/5] RISC-V: Allow RVV register overlap for vfw{add, ... pan2 . li
- [PATCH v1 1/5] RISC-V: Allow RVV register overlap for vfw{... pan2 . li
- Re: [PATCH v1 1/5] RISC-V: Allow RVV register overlap ... Robin Dapp
- [PATCH v1 4/5] RISC-V: Add test cases for vfwmul.vf reg ov... pan2 . li
- [PATCH v1 2/5] RISC-V: Add test cases for vfwadd.vf reg ov... pan2 . li
- [PATCH v1 3/5] RISC-V: Add test cases for vfwsub.vf reg ov... pan2 . li
- [PATCH v1 5/5] RISC-V: Remove xfail of the vfwadd.vf reg o... pan2 . li
