Port the SHA512 intrinsics (FEAT_SHA3) to the pragma-based framework and add
assembly tests for each intrinsic.
gcc/ChangeLog:
* config/aarch64/aarch64-neon-builtins-base.cc: New function
bases.
* config/aarch64/aarch64-neon-builtins-base.def (vsha512hq,
vsha512h2q, vsha512su0q, vsha512su1q): New function
declarations.
* config/aarch64/aarch64-simd-builtins.def: Delete builtin
functions.
* config/aarch64/arm_neon.h (vsha512hq_u64, vsha512h2q_u64,
vsha512su0q_u64, vsha512su1q_u64): Delete functions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/neon/vsha512.c: New test.
---
.../aarch64/aarch64-neon-builtins-base.cc | 6 ++++
.../aarch64/aarch64-neon-builtins-base.def | 8 +++++
gcc/config/aarch64/aarch64-simd-builtins.def | 8 -----
gcc/config/aarch64/arm_neon.h | 28 ----------------
.../gcc.target/aarch64/neon/vsha512.c | 32 +++++++++++++++++++
5 files changed, 46 insertions(+), 36 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vsha512.c
diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc
b/gcc/config/aarch64/aarch64-neon-builtins-base.cc
index f4099e99d1e..b6ec01704e1 100644
--- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc
@@ -811,4 +811,10 @@ NEON_FUNCTION (vsha256hq,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256hv4s
NEON_FUNCTION (vsha256h2q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256h2v4si>,)
NEON_FUNCTION (vsha256su0q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256su0v4si>,)
NEON_FUNCTION (vsha256su1q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256su1v4si>,)
+
+// SHA512
+NEON_FUNCTION (vsha512hq,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512hqv2di>,)
+NEON_FUNCTION (vsha512h2q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512h2qv2di>,)
+NEON_FUNCTION (vsha512su0q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512su0qv2di>,)
+NEON_FUNCTION (vsha512su1q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha512su1qv2di>,)
}
diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def
b/gcc/config/aarch64/aarch64-neon-builtins-base.def
index 50ddb078135..48f4c73897e 100644
--- a/gcc/config/aarch64/aarch64-neon-builtins-base.def
+++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def
@@ -170,4 +170,12 @@ DEF_NEON_FUNCTION (vsha256hq, s_unsigned,
("Q0,Q0,Q0,Q0"))
DEF_NEON_FUNCTION (vsha256h2q, s_unsigned, ("Q0,Q0,Q0,Q0"))
DEF_NEON_FUNCTION (vsha256su0q, s_unsigned, ("Q0,Q0,Q0"))
DEF_NEON_FUNCTION (vsha256su1q, s_unsigned, ("Q0,Q0,Q0,Q0"))
+#undef REQUIRED_EXTENSIONS
+
+// SHA512
+#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD |
AARCH64_FL_SHA2)
+DEF_NEON_FUNCTION (vsha512hq, d_unsigned, ("Q0,Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vsha512h2q, d_unsigned, ("Q0,Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vsha512su0q, d_unsigned, ("Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vsha512su1q, d_unsigned, ("Q0,Q0,Q0,Q0"))
#undef REQUIRED_EXTENSIONS
\ No newline at end of file
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 7c055cdb7e6..d6ca018c7e8 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -845,14 +845,6 @@
VAR1 (BINOPU, sm4eq, 0, DEFAULT, v4si)
/* Implemented by aarch64_sm4ekeyqv4si. */
VAR1 (BINOPU, sm4ekeyq, 0, DEFAULT, v4si)
- /* Implemented by aarch64_crypto_sha512hqv2di. */
- VAR1 (TERNOPU, crypto_sha512hq, 0, DEFAULT, v2di)
- /* Implemented by aarch64_sha512h2qv2di. */
- VAR1 (TERNOPU, crypto_sha512h2q, 0, DEFAULT, v2di)
- /* Implemented by aarch64_crypto_sha512su0qv2di. */
- VAR1 (BINOPU, crypto_sha512su0q, 0, DEFAULT, v2di)
- /* Implemented by aarch64_crypto_sha512su1qv2di. */
- VAR1 (TERNOPU, crypto_sha512su1q, 0, DEFAULT, v2di)
/* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>. */
VAR1 (TERNOP, fmlal_low, 0, FP, v2sf)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 89b28778962..a9b325cebde 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -20938,34 +20938,6 @@ vsm4ekeyq_u32 (uint32x4_t __a, uint32x4_t __b)
#pragma GCC push_options
#pragma GCC target ("+nothing+sha3")
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha512hq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
-{
- return __builtin_aarch64_crypto_sha512hqv2di_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha512h2q_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
-{
- return __builtin_aarch64_crypto_sha512h2qv2di_uuuu (__a, __b, __c);
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha512su0q_u64 (uint64x2_t __a, uint64x2_t __b)
-{
- return __builtin_aarch64_crypto_sha512su0qv2di_uuu (__a, __b);
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha512su1q_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
-{
- return __builtin_aarch64_crypto_sha512su1qv2di_uuuu (__a, __b, __c);
-}
-
#pragma GCC pop_options
/* AdvSIMD Complex numbers intrinsics. */
diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vsha512.c
b/gcc/testsuite/gcc.target/aarch64/neon/vsha512.c
new file mode 100644
index 00000000000..5cad5c9b34a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neon/vsha512.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_neon_test.h"
+
+/*
+** test_vsha512hq_u64:
+** sha512h q0, q1, v2\.2d
+** ret
+*/
+TEST_UNIFORM_TERNARY (vsha512hq_u64, uint64x2_t)
+
+/*
+** test_vsha512h2q_u64:
+** sha512h2 q0, q1, v2\.2d
+** ret
+*/
+TEST_UNIFORM_TERNARY (vsha512h2q_u64, uint64x2_t)
+
+/*
+** test_vsha512su0q_u64:
+** sha512su0 v0\.2d, v1\.2d
+** ret
+*/
+TEST_UNIFORM_BINARY (vsha512su0q_u64, uint64x2_t)
+
+/*
+** test_vsha512su1q_u64:
+** sha512su1 v0\.2d, v1\.2d, v2\.2d
+** ret
+*/
+TEST_UNIFORM_TERNARY (vsha512su1q_u64, uint64x2_t)
--
2.51.0
