Port the SHA256 intrinsics (FEAT_SHA2) to the pragma-based framework and add
assembly tests for each intrinsic.
gcc/ChangeLog:
* config/aarch64/aarch64-neon-builtins-base.cc: New function
bases.
* config/aarch64/aarch64-neon-builtins-base.def (vsha256hq,
vsha256h2q, vsha256su0q, vsha256su1q): New function
definitions.
* config/aarch64/aarch64-simd-builtins.def: Delete builtin
functions
* config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32,
vsha256su0q_u32, vsha256su1q_u32): Delete functions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/neon/vsha256.c: New test.
---
.../aarch64/aarch64-neon-builtins-base.cc | 6 +++
.../aarch64/aarch64-neon-builtins-base.def | 8 ++++
gcc/config/aarch64/aarch64-simd-builtins.def | 9 +----
gcc/config/aarch64/arm_neon.h | 38 -------------------
.../gcc.target/aarch64/neon/vsha256.c | 32 ++++++++++++++++
5 files changed, 47 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vsha256.c
diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.cc
b/gcc/config/aarch64/aarch64-neon-builtins-base.cc
index ef128d0de1d..f4099e99d1e 100644
--- a/gcc/config/aarch64/aarch64-neon-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-neon-builtins-base.cc
@@ -805,4 +805,10 @@ NEON_FUNCTION (vsha1pq,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1pv4si>,)
NEON_FUNCTION (vsha1h, gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1hsi>,)
NEON_FUNCTION (vsha1su0q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1su0v4si>,)
NEON_FUNCTION (vsha1su1q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha1su1v4si>,)
+
+// SHA256
+NEON_FUNCTION (vsha256hq,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256hv4si>,)
+NEON_FUNCTION (vsha256h2q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256h2v4si>,)
+NEON_FUNCTION (vsha256su0q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256su0v4si>,)
+NEON_FUNCTION (vsha256su1q,
gimple_exact_insn<CODE_FOR_aarch64_crypto_sha256su1v4si>,)
}
diff --git a/gcc/config/aarch64/aarch64-neon-builtins-base.def
b/gcc/config/aarch64/aarch64-neon-builtins-base.def
index b0cc6d1ce92..50ddb078135 100644
--- a/gcc/config/aarch64/aarch64-neon-builtins-base.def
+++ b/gcc/config/aarch64/aarch64-neon-builtins-base.def
@@ -162,4 +162,12 @@ DEF_NEON_FUNCTION (vsha1pq, s_unsigned, ("Q0,Q0,s0,Q0"))
DEF_NEON_FUNCTION (vsha1h, s_unsigned, ("s0,s0"))
DEF_NEON_FUNCTION (vsha1su0q, s_unsigned, ("Q0,Q0,Q0,Q0"))
DEF_NEON_FUNCTION (vsha1su1q, s_unsigned, ("Q0,Q0,Q0"))
+#undef REQUIRED_EXTENSIONS
+
+// SHA256
+#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD |
AARCH64_FL_SHA2)
+DEF_NEON_FUNCTION (vsha256hq, s_unsigned, ("Q0,Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vsha256h2q, s_unsigned, ("Q0,Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vsha256su0q, s_unsigned, ("Q0,Q0,Q0"))
+DEF_NEON_FUNCTION (vsha256su1q, s_unsigned, ("Q0,Q0,Q0,Q0"))
#undef REQUIRED_EXTENSIONS
\ No newline at end of file
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 11d418a68a4..7c055cdb7e6 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -711,14 +711,7 @@
BUILTIN_VDQSF (QUADOP_LANE, float_mls_lane, 0, FP)
BUILTIN_VDQSF (QUADOP_LANE, float_mla_laneq, 0, FP)
BUILTIN_VDQSF (QUADOP_LANE, float_mls_laneq, 0, FP)
-
- /* Implemented by aarch64_crypto_sha256<op><mode>. */
- VAR1 (TERNOPU, crypto_sha256h, 0, DEFAULT, v4si)
- VAR1 (TERNOPU, crypto_sha256h2, 0, DEFAULT, v4si)
- VAR1 (BINOPU, crypto_sha256su0, 0, DEFAULT, v4si)
- VAR1 (TERNOPU, crypto_sha256su1, 0, DEFAULT, v4si)
-
- /* Implemented by aarch64_crypto_pmull<mode>. */
+ /* Implemented by aarch64_crypto_pmull<mode>. */
VAR1 (BINOPP, crypto_pmull, 0, DEFAULT, di)
VAR1 (BINOPP, crypto_pmull, 0, DEFAULT, v2di)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index b851f046bcb..89b28778962 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -16723,44 +16723,6 @@ vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int
__c)
return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
}
-#pragma GCC push_options
-#pragma GCC target ("+nothing+sha2")
-
-/* vsha1 */
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha256hq_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
-{
- return __builtin_aarch64_crypto_sha256hv4si_uuuu (__hash_abcd, __hash_efgh,
- __wk);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha256h2q_u32 (uint32x4_t __hash_efgh, uint32x4_t __hash_abcd, uint32x4_t
__wk)
-{
- return __builtin_aarch64_crypto_sha256h2v4si_uuuu (__hash_efgh, __hash_abcd,
- __wk);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha256su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7)
-{
- return __builtin_aarch64_crypto_sha256su0v4si_uuu (__w0_3, __w4_7);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15)
-{
- return __builtin_aarch64_crypto_sha256su1v4si_uuuu (__tw0_3, __w8_11,
- __w12_15);
-}
-
-#pragma GCC pop_options
-
/* vshl */
__extension__ extern __inline int8x8_t
diff --git a/gcc/testsuite/gcc.target/aarch64/neon/vsha256.c
b/gcc/testsuite/gcc.target/aarch64/neon/vsha256.c
new file mode 100644
index 00000000000..a270e830b6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neon/vsha256.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_neon_test.h"
+
+/*
+** test_vsha256hq_u32:
+** sha256h q0, q1, v2\.4s
+** ret
+*/
+TEST_UNIFORM_TERNARY (vsha256hq_u32, uint32x4_t)
+
+/*
+** test_vsha256h2q_u32:
+** sha256h2 q0, q1, v2\.4s
+** ret
+*/
+TEST_UNIFORM_TERNARY (vsha256h2q_u32, uint32x4_t)
+
+/*
+** test_vsha256su0q_u32:
+** sha256su0 v0\.4s, v1\.4s
+** ret
+*/
+TEST_UNIFORM_BINARY (vsha256su0q_u32, uint32x4_t)
+
+/*
+** test_vsha256su1q_u32:
+** sha256su1 v0\.4s, v1\.4s, v2\.4s
+** ret
+*/
+TEST_UNIFORM_TERNARY (vsha256su1q_u32, uint32x4_t)
--
2.51.0
