Hello,
Changes from v1:
- v1 was a series of two patches. Merge them into a single
patch and rebase on top of the multiple gating predicates
patch.
- Drop the rs6000-builtin.cc change for ENB_P8V and the split of
the power8-vector stanza into [power8, altivec] and
[power8, vsx] since the multiple gating predicates patch makes
both unnecessary.
This patch can only be applied after the patch that adds support for
multiple gating predicates on built-in stanzas:
https://patchwork.ozlabs.org/project/gcc/patch/
[email protected]/
Below patch is bootstrapped and regtested on powerpc64le-linux with no
regressions.
Thank You,
Kishan
TARGET_P8_VECTOR is redundant: it is always set together with
TARGET_POWER8 and TARGET_VSX. This patch removes the P8_VECTOR ISA
mask from rs6000_isa_flags and replaces every use of TARGET_P8_VECTOR
with TARGET_POWER8 && TARGET_VSX, TARGET_POWER8 && TARGET_ALTIVEC or
TARGET_POWER8, according to the context. -mpower8-vector stays as a
plain WarnRemoved option that is no longer tied to an ISA mask.
The patch adapts to the multiple gating predicates support for built-in
stanzas. With it, ENB_P8V is no longer needed, because the stanzas use
explicit [power8, vsx] predicates, so the rs6000-builtin.cc changes of
the original series are dropped.
This patch only covers the Power8 part. The Power9 and Power10 work is
still to be done, so this does not resolve PR target/116266 entirely.
The testcase in the PR targets Power10 and will still fail.
2026-10-20 Manjunath S Matti <[email protected]>
gcc/ChangeLog:
PR target/116266
* config/rs6000/altivec.md (*vspltisw_v2di_split): Move here from
vsx.md. Replace TARGET_P8_VECTOR with TARGET_POWER8 &&
TARGET_ALTIVEC.
(mulv4si3_p8, altivec_vmsumudm, p8_vmrgew_<mode>, p8_vmrgow_<mode>,
p8_vmrgew_<mode>_direct, p8_vmrgow_<mode>_direct,
vec_widen_umult_even_v4si, vec_widen_smult_even_v4si,
vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si,
altivec_vmuleuw, altivec_vmulouw, altivec_vmulesw, altivec_vmulosw,
altivec_vpermxor, *p8v_clz<mode>2, *p8v_popcount<mode>2, p8v_vgbbd,
altivec_vbpermq, altivec_vbpermq2, bcd<bcd_add_sub>_<mode>,
*bcd<bcd_add_sub>_test_<mode>, *bcd<bcd_add_sub>_test2_<mode>,
bcd<bcd_add_sub>_<code>_<mode>, *bcdinvalid_<mode>,
bcdinvalid_<mode>, bcdshift_v16qi, define_peephole2 to combine a
bcdadd/bcdsub, VSHIFT_MODE iterator, vector shift patterns): Replace
TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_ALTIVEC.
(mulv4si3): Replace TARGET_P8_VECTOR with TARGET_POWER8.
* config/rs6000/constraints.md (wB): Replace TARGET_P8_VECTOR with
TARGET_POWER8 && TARGET_ALTIVEC.
(wM): Replace TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_VSX.
* config/rs6000/crypto.md (crypto_vpmsum<CR_char>,
crypto_vpermxor_<mode>): Replace TARGET_P8_VECTOR with
TARGET_POWER8 && TARGET_ALTIVEC.
* config/rs6000/predicates.md (vector_shift_constant): Replace
TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_VSX.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Remove
stale comments about OPTION_MASK_P8_VECTOR. Replace the check for
OPTION_MASK_P8_VECTOR with checks for OPTION_MASK_POWER8 and
OPTION_MASK_VSX.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER)
(OTHER_VSX_VECTOR_MASKS, POWERPC_MASKS): Remove
OPTION_MASK_P8_VECTOR.
* config/rs6000/rs6000-string.cc (emit_final_compare_vec): Replace
TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_VSX.
(expand_block_compare, expand_strn_compare): Replace
TARGET_P8_VECTOR with TARGET_POWER8. Update comments.
* config/rs6000/rs6000.cc (rs6000_clone_map): Use
OPTION_MASK_POWER8 for arch_2_07.
(rs6000_setup_reg_addr_masks): Replace !TARGET_P8_VECTOR with
!TARGET_VSX || !TARGET_POWER8.
(rs6000_init_hard_regno_mode_ok): Replace TARGET_P8_VECTOR with
TARGET_POWER8 for rs6000_vector_unit and with TARGET_POWER8 &&
TARGET_VSX elsewhere.
(rs6000_option_override_internal): Remove OPTION_MASK_P8_VECTOR
uses. Simplify TARGET_P8_VECTOR || TARGET_POWER8 to TARGET_POWER8.
Remove the handling of TARGET_P8_VECTOR without TARGET_VSX. Check
!TARGET_VSX instead of !TARGET_P8_VECTOR when clearing
OPTION_MASK_P9_VECTOR. Replace TARGET_P8_VECTOR with TARGET_POWER8
&& TARGET_VSX for TARGET_ALLOW_MOVMISALIGN.
(vspltisw_vupkhsw_constant_p): Replace the !TARGET_P8_VECTOR check
with !TARGET_POWER8 and !TARGET_ALTIVEC checks.
(output_vec_const_move, rs6000_expand_vector_init)
(rs6000_secondary_reload_simple_move)
(rs6000_preferred_reload_class): Replace TARGET_P8_VECTOR with
TARGET_POWER8 && TARGET_VSX.
(rs6000_expand_vector_set, altivec_expand_vec_perm_le): Replace
TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_ALTIVEC.
(altivec_expand_vec_perm_const): Replace OPTION_MASK_P8_VECTOR with
OPTION_MASK_VSX | OPTION_MASK_POWER8. Require all bits of the
pattern mask to be set in rs6000_isa_flags.
(rs6000_opt_masks): Remove entry for power8-vector.
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE, TARGET_XSCVDPSPN)
(TARGET_XSCVSPDPN): Replace TARGET_P8_VECTOR with TARGET_POWER8 &&
TARGET_VSX.
(TARGET_VADDUQM): Replace TARGET_P8_VECTOR with TARGET_POWER8 &&
TARGET_ALTIVEC.
* config/rs6000/rs6000.md (isa attr p8v, ALTIVEC_DFORM): Replace
TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_VSX.
(floatsi<mode>2_lfiwax_mem, floatunssi<mode>2_lfiwzx_mem)
(*fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem, fixuns_trunc<mode>si2)
(define_split for SI to DI sign_extend, define_peephole2 for SF
register move): Likewise.
(eqv<mode>3, nand<mode>3, iorn<mode>3, *boolc<mode>3_internal1)
(*boolc<mode>3_internal2, *boolcc<mode>3_internal1)
(*boolcc<mode>3_internal2, *eqv<mode>3_internal1)
(*eqv<mode>3_internal2): Replace TARGET_P8_VECTOR with TARGET_POWER8
&& TARGET_ALTIVEC. Simplify the split condition using "&&".
* config/rs6000/rs6000.opt (mpower8-vector): Remove Mask and Var.
* config/rs6000/vector.md (clz<mode>2, popcount<mode>2): Replace
TARGET_P8_VECTOR with TARGET_POWER8 && TARGET_ALTIVEC.
* config/rs6000/vsx.md (*vspltisw_v2di_split): Move to altivec.md.
gcc/testsuite/ChangeLog:
PR target/116266
* gcc.target/powerpc/pragma_misc9.c (test3): Update the expected
dg-error message, replacing '-mvsx' with '-maltivec'.
Co-authored-by: Kishan Parmar <[email protected]>
---
gcc/config/rs6000/altivec.md | 90 ++++++++++++-------
gcc/config/rs6000/constraints.md | 4 +-
gcc/config/rs6000/crypto.md | 4 +-
gcc/config/rs6000/predicates.md | 2 +-
gcc/config/rs6000/rs6000-builtins.def | 7 +-
gcc/config/rs6000/rs6000-c.cc | 35 +-------
gcc/config/rs6000/rs6000-cpus.def | 3 -
gcc/config/rs6000/rs6000-string.cc | 14 +--
gcc/config/rs6000/rs6000.cc | 48 +++++-----
gcc/config/rs6000/rs6000.h | 10 +--
gcc/config/rs6000/rs6000.md | 53 +++++------
gcc/config/rs6000/rs6000.opt | 2 +-
gcc/config/rs6000/vector.md | 4 +-
gcc/config/rs6000/vsx.md | 24 -----
.../gcc.target/powerpc/pragma_misc9.c | 2 +-
15 files changed, 137 insertions(+), 165 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7e185f59c84..87bb331d015 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -836,7 +836,7 @@
[(set (match_operand:V4SI 0 "register_operand" "=v")
(mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmuluwm %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -855,7 +855,7 @@
rtx low_product;
rtx high_product;
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8)
{
emit_insn (gen_mulv4si3_p8 (operands[0], operands[1], operands[2]));
DONE;
@@ -1054,7 +1054,7 @@
(match_operand:V2DI 2 "register_operand" "v")
(match_operand:V1TI 3 "register_operand" "v")]
UNSPEC_VMSUMUDM))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmsumudm %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -1520,7 +1520,7 @@
(match_operand:VSX_W 2 "register_operand" "v"))
(parallel [(const_int 0) (const_int 4)
(const_int 2) (const_int 6)])))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (BYTES_BIG_ENDIAN)
return "vmrgew %0,%1,%2";
@@ -1537,7 +1537,7 @@
(match_operand:VSX_W 2 "register_operand" "v"))
(parallel [(const_int 1) (const_int 5)
(const_int 3) (const_int 7)])))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (BYTES_BIG_ENDIAN)
return "vmrgow %0,%1,%2";
@@ -1568,7 +1568,7 @@
(unspec:VSX_W [(match_operand:VSX_W 1 "register_operand" "v")
(match_operand:VSX_W 2 "register_operand" "v")]
UNSPEC_VMRGEW_DIRECT))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmrgew %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -1577,7 +1577,7 @@
(unspec:VSX_W [(match_operand:VSX_W 1 "register_operand" "v")
(match_operand:VSX_W 2 "register_operand" "v")]
UNSPEC_VMRGOW_DIRECT))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmrgow %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -1637,7 +1637,7 @@
[(use (match_operand:V2DI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_altivec_vmuleuw (operands[0], operands[1], operands[2]));
@@ -1663,7 +1663,7 @@
[(use (match_operand:V2DI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_altivec_vmulesw (operands[0], operands[1], operands[2]));
@@ -1741,7 +1741,7 @@
[(use (match_operand:V2DI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_altivec_vmulouw (operands[0], operands[1], operands[2]));
@@ -1767,7 +1767,7 @@
[(use (match_operand:V2DI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_altivec_vmulosw (operands[0], operands[1], operands[2]));
@@ -1866,7 +1866,7 @@
(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VMULEUW))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmuleuw %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1884,7 +1884,7 @@
(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VMULOUW))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmulouw %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1902,7 +1902,7 @@
(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VMULESW))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmulesw %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1920,7 +1920,7 @@
(unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VMULOSW))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vmulosw %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -2217,7 +2217,7 @@
;; VSPLTISW or XXSPLTIB to load up the constant, and not worry about the bits
;; that the vector shift instructions will not use.
(define_mode_iterator VSHIFT_MODE [(V4SI "TARGET_P9_VECTOR")
- (V2DI "TARGET_P8_VECTOR")])
+ (V2DI "TARGET_POWER8 &&
TARGET_ALTIVEC")])
(define_code_iterator vshift_code [ashift ashiftrt lshiftrt])
(define_code_attr vshift_attr [(ashift "ashift")
@@ -2230,7 +2230,7 @@
(match_operand:VSHIFT_MODE 1 "register_operand" "v")
(match_operand:VSHIFT_MODE 2 "vector_shift_constant" "")))
(clobber (match_scratch:VSHIFT_MODE 3 "=&v"))]
- "((<MODE>mode == V2DImode && TARGET_P8_VECTOR)
+ "((<MODE>mode == V2DImode && TARGET_POWER8 && TARGET_ALTIVEC)
|| (<MODE>mode == V4SImode && TARGET_P9_VECTOR))"
"#"
"&& 1"
@@ -2252,7 +2252,7 @@
[(set (match_operand:VSHIFT_MODE 0 "register_operand" "=v")
(unspec:VSHIFT_MODE [(match_operand 1 "const_int_operand" "n")]
UNSPEC_VECTOR_SHIFT))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (UINTVAL (operands[1]) <= 15)
return "vspltisw %0,%1";
@@ -2790,6 +2790,32 @@
}
[(set_attr "type" "vecperm")])
+(define_insn_and_split "*vspltisw_v2di_split"
+ [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
+ (match_operand:V2DI 1 "vspltisw_vupkhsw_constant_split" "W"))]
+ "TARGET_POWER8 && TARGET_ALTIVEC
+ && vspltisw_vupkhsw_constant_split (operands[1], V2DImode)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+ rtx tmp = can_create_pseudo_p ()
+ ? gen_reg_rtx (V4SImode)
+ : gen_lowpart (V4SImode, op0);
+ int value;
+
+ vspltisw_vupkhsw_constant_p (op1, V2DImode, &value);
+ emit_insn (gen_altivec_vspltisw (tmp, GEN_INT (value)));
+ emit_insn (gen_altivec_vupkhsw_direct (op0, tmp));
+
+ DONE;
+}
+ [(set_attr "type" "vecperm")
+ (set_attr "length" "8")])
+
+
/* The cbranch_optab doesn't allow FAIL, so old cpus which are
inefficient on unaligned vsx are disabled as the cost is high
for unaligned load/store. */
@@ -4168,7 +4194,7 @@
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))
(use (match_operand:V16QI 3 "register_operand"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (!BYTES_BIG_ENDIAN)
{
@@ -4400,7 +4426,7 @@
(define_insn "*p8v_clz<mode>2"
[(set (match_operand:VI2 0 "register_operand" "=v")
(clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vclz<wd> %0,%1"
[(set_attr "type" "vecsimple")])
@@ -4430,7 +4456,7 @@
(define_insn "*p8v_popcount<mode>2"
[(set (match_operand:VI2 0 "register_operand" "=v")
(popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vpopcnt<wd> %0,%1"
[(set_attr "type" "vecsimple")])
@@ -4449,7 +4475,7 @@
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VGBBD))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vgbbd %0,%1"
[(set_attr "type" "vecsimple")])
@@ -4540,7 +4566,7 @@
(unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VBPERMQ))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vbpermq %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -4550,7 +4576,7 @@
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VBPERMQ))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vbpermq %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -4622,7 +4648,7 @@
(match_operand:QI 3 "const_0_to_1_operand" "n")]
UNSPEC_BCD_ADD_SUB))
(clobber (reg:CCFP CR6_REGNO))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
@@ -4640,7 +4666,7 @@
UNSPEC_BCD_ADD_SUB)
(match_operand:V2DF 4 "zero_constant" "j")))
(clobber (match_scratch:VBCD 0 "=v"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
@@ -4657,7 +4683,7 @@
(match_dup 3)]
UNSPEC_BCD_ADD_SUB)
(match_operand:V2DF 4 "zero_constant" "j")))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
@@ -4755,7 +4781,7 @@
(set (match_operand:SI 0 "register_operand")
(BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
operands[4] = CONST0_RTX (V2DFmode);
})
@@ -4767,7 +4793,7 @@
UNSPEC_BCDSUB)
(match_operand:V2DF 2 "zero_constant" "j")))
(clobber (match_scratch:VBCD 0 "=v"))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"bcdsub. %0,%1,%1,0"
[(set_attr "type" "vecsimple")])
@@ -4781,7 +4807,7 @@
(set (match_operand:SI 0 "register_operand")
(unordered:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
operands[2] = CONST0_RTX (V2DFmode);
})
@@ -4793,7 +4819,7 @@
(match_operand:QI 3 "const_0_to_1_operand" "n")]
UNSPEC_BCDSHIFT))
(clobber (reg:CCFP CR6_REGNO))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"bcds. %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
@@ -4849,7 +4875,7 @@
UNSPEC_BCD_ADD_SUB)
(match_operand:V2DF 4 "zero_constant")))
(clobber (match_operand:V1TI 5 "register_operand"))])]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
[(parallel [(set (match_dup 0)
(unspec:V1TI [(match_dup 1)
(match_dup 2)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4b2e703f049..a36a8c0938a 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -108,7 +108,7 @@
"@internal Signed 5-bit constant integer that can be loaded into an
Altivec register."
(and (match_code "const_int")
- (match_test "TARGET_P8_VECTOR")
+ (match_test "TARGET_POWER8 && TARGET_ALTIVEC")
(match_operand 0 "s5bit_cint_operand")))
(define_constraint "wE"
@@ -131,7 +131,7 @@
(define_constraint "wM"
"@internal Match vector constant with all 1's if the XXLORC instruction
is available."
- (and (match_test "TARGET_P8_VECTOR")
+ (and (match_test "TARGET_POWER8 && TARGET_VSX")
(match_operand 0 "all_ones_constant")))
;; ISA 3.0 vector d-form addresses
diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md
index a25d9f75439..7e3375fb08a 100644
--- a/gcc/config/rs6000/crypto.md
+++ b/gcc/config/rs6000/crypto.md
@@ -126,7 +126,7 @@
(unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
(match_operand:CR_mode 2 "register_operand" "v")]
UNSPEC_VPMSUM))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vpmsum<CR_char> %0,%1,%2"
[(set_attr "type" "crypto")])
@@ -137,7 +137,7 @@
(match_operand:CR_mode 2 "register_operand" "v")
(match_operand:CR_mode 3 "register_operand" "v")]
UNSPEC_VPERMXOR))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
"vpermxor %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index a6ec04f5922..0368f85e797 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -927,7 +927,7 @@
if (mode == V2DImode)
{
min_value = 0;
- if (!TARGET_P8_VECTOR)
+ if (!(TARGET_POWER8 && TARGET_VSX))
return 0;
}
else if (mode == V4SImode)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 6cc9f82ae7d..967f8cf017c 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1881,8 +1881,9 @@
; Power8 vector built-ins.
-; PR125389: was [power8-vector]; split into explicit predicates [power8, vsx].
-[power8, vsx]
+; PR125389: was [power8-vector]; split into explicit predicates
+; [power8, altivec] and [power8, vsx].
+[power8, altivec]
const vsll __builtin_altivec_abs_v2di (vsll);
ABS_V2DI absv2di2 {}
@@ -2279,6 +2280,8 @@
const vui __builtin_crypto_vpmsumw (vui, vui);
VPMSUMW crypto_vpmsumw {}
+; Power8 vsx built-ins.
+[power8, vsx]
const vf __builtin_vsx_float2_v2df (vd, vd);
FLOAT2_V2DF float2_v2df {}
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index f51593e0455..bca22de2f17 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -475,12 +475,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
if (rs6000_aix_extabi)
rs6000_define_or_undefine_macro (define_p, "__EXTABI__");
}
- /* Note that the OPTION_MASK_VSX flag is automatically turned on in
- the following conditions:
- 1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
- was not explicitly turned off. Hereafter, the OPTION_MASK_VSX
- flag is considered to have been explicitly turned on.
- Note that the OPTION_MASK_VSX flag is automatically turned off in
+ /* Note that the OPTION_MASK_VSX flag is automatically turned off in
the following conditions:
1. The operating system does not support saving of AltiVec
registers (OS_MISSING_ALTIVEC).
@@ -509,33 +504,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
/* Tell the user that our HTM insn patterns act as memory barriers. */
rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
}
- /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
- on in the following conditions:
- 1. TARGET_P9_VECTOR is explicitly turned on and
- OPTION_MASK_P8_VECTOR is not explicitly turned off.
- Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
- have been turned off explicitly.
- Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
- off in the following conditions:
- 1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
- were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
- not turned on explicitly.
- 2. If TARGET_ALTIVEC is turned off. Hereafter, the
- OPTION_MASK_P8_VECTOR flag is considered to have been turned off
- explicitly.
- 3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
- explicitly enabled. If TARGET_VSX is explicitly enabled, the
- OPTION_MASK_P8_VECTOR flag is hereafter also considered to
- have been turned off explicitly. */
- if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+ if ((flags & OPTION_MASK_POWER8) != 0 && (flags & OPTION_MASK_VSX) != 0)
rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
- /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
- off in the following conditions:
- 1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
- not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
- was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
- also considered to have been turned off explicitly.
- Note that the OPTION_MASK_P9_VECTOR is automatically turned on
+ /* Note that the OPTION_MASK_P9_VECTOR is automatically turned on
in the following conditions:
1. If TARGET_P9_MINMAX was turned on explicitly.
Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 4dcdcf7c858..bb8ff2724b7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -48,7 +48,6 @@
system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
| OPTION_MASK_POWER8 \
- | OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_QUAD_MEMORY \
@@ -98,7 +97,6 @@
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
- | OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_FLOAT128_HW \
@@ -146,7 +144,6 @@
| OPTION_MASK_NO_UPDATE \
| OPTION_MASK_POWER8 \
| OPTION_MASK_P8_FUSION \
- | OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR \
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 062ff1e2465..d7b187a292e 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -847,7 +847,7 @@ emit_final_compare_vec (rtx str1, rtx str2, rtx result,
}
else
{
- gcc_assert (TARGET_P8_VECTOR);
+ gcc_assert (TARGET_POWER8 && TARGET_VSX);
rtx diffix = gen_reg_rtx (DImode);
rtx result_gbbd = gen_reg_rtx (V16QImode);
/* Since each byte of the input is either 00 or FF, the bytes in
@@ -2005,10 +2005,10 @@ expand_block_compare (rtx operands[])
at least POWER8. That way we can rely on overlapping compares to
do the final comparison of less than 16 bytes. Also I do not
want to deal with making this work for 32 bits. In addition, we
- have to make sure that we have at least P8_VECTOR (we don't allow
- P9_VECTOR without P8_VECTOR). */
+ have to make sure that we have at least P8 vector support (we
+ don't allow P9 vector without P8 vector support). */
int use_vec = (bytes >= 33 && !TARGET_32BIT
- && TARGET_EFFICIENT_UNALIGNED_VSX && TARGET_P8_VECTOR);
+ && TARGET_EFFICIENT_UNALIGNED_VSX && TARGET_POWER8);
/* We don't want to generate too much code. The loop code can take
over for lengths greater than 31 bytes. */
@@ -2473,10 +2473,10 @@ expand_strn_compare (rtx operands[], int no_length)
at least POWER8. That way we can rely on overlapping compares to
do the final comparison of less than 16 bytes. Also I do not
want to deal with making this work for 32 bits. In addition, we
- have to make sure that we have at least P8_VECTOR (we don't allow
- P9_VECTOR without P8_VECTOR). */
+ have to make sure that we have at least P8 vector support (we
+ don't allow P9 vector without P8 vector support). */
int use_vec = (bytes >= 16 && !TARGET_32BIT
- && TARGET_EFFICIENT_UNALIGNED_VSX && TARGET_P8_VECTOR);
+ && TARGET_EFFICIENT_UNALIGNED_VSX && TARGET_POWER8);
if (use_vec)
required_align = 16;
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8cfc8183b83..9bc9fddd730 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -259,7 +259,7 @@ static const struct clone_map rs6000_clone_map[CLONE_MAX] =
{
{ 0, "" }, /* Default options. */
{ OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
{ OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
- { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
+ { OPTION_MASK_POWER8, "arch_2_07" }, /* ISA 2.07 (power8).
*/
{ OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */
{ OPTION_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
};
@@ -2723,7 +2723,7 @@ rs6000_setup_reg_addr_masks (void)
&& !VECTOR_ALIGNMENT_P (m2)
&& !complex_p
&& (m != E_DFmode || !TARGET_VSX)
- && (m != E_SFmode || !TARGET_P8_VECTOR)
+ && (m != E_SFmode || !TARGET_VSX || !TARGET_POWER8)
&& !small_int_vsx_p)
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
@@ -2968,12 +2968,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
{
rs6000_vector_mem[V2DImode] = VECTOR_VSX;
rs6000_vector_unit[V2DImode]
- = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
+ = (TARGET_POWER8) ? VECTOR_P8_VECTOR : VECTOR_NONE;
rs6000_vector_align[V2DImode] = align64;
rs6000_vector_mem[V1TImode] = VECTOR_VSX;
rs6000_vector_unit[V1TImode]
- = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
+ = (TARGET_POWER8) ? VECTOR_P8_VECTOR : VECTOR_NONE;
rs6000_vector_align[V1TImode] = 128;
}
@@ -2986,7 +2986,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
}
/* SFmode, see if we want to use the VSX unit. */
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8 && TARGET_VSX)
{
rs6000_vector_unit[SFmode] = VECTOR_VSX;
rs6000_vector_align[SFmode] = 32;
@@ -3209,7 +3209,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[DFmode].scalar_in_vmx_p = true;
reg_addr[DImode].scalar_in_vmx_p = true;
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8 && TARGET_VSX)
{
reg_addr[SFmode].scalar_in_vmx_p = true;
reg_addr[SImode].scalar_in_vmx_p = true;
@@ -3938,8 +3938,7 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX)) != 0)
- rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO)
- & ~rs6000_isa_flags_explicit);
+ rs6000_isa_flags &= ~(OPTION_MASK_CRYPTO & ~rs6000_isa_flags_explicit);
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
@@ -3982,7 +3981,7 @@ rs6000_option_override_internal (bool global_init_p)
else
rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
}
- else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
+ else if (TARGET_POWER8 || TARGET_CRYPTO)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
@@ -4031,9 +4030,6 @@ rs6000_option_override_internal (bool global_init_p)
based on either !TARGET_VSX or !TARGET_ALTIVEC concise. */
gcc_assert (TARGET_ALTIVEC || !TARGET_VSX);
- if (TARGET_P8_VECTOR && !TARGET_VSX)
- rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
-
if (TARGET_DFP && !TARGET_HARD_FLOAT)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
@@ -4118,14 +4114,14 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
/* ISA 3.0 vector instructions include ISA 2.07. */
- if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
+ if (TARGET_P9_VECTOR && !TARGET_VSX)
rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
support. If we only have ISA 2.06 support, and the user did not specify
the switch, leave it set to -1 so the movmisalign patterns are enabled,
but we don't enable the full vectorization support */
- if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR)
+ if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_POWER8 && TARGET_VSX)
TARGET_ALLOW_MOVMISALIGN = 1;
else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
@@ -6739,7 +6735,10 @@ vspltisw_vupkhsw_constant_p (rtx op, machine_mode mode,
int *constant_ptr)
HOST_WIDE_INT value;
rtx elt;
- if (!TARGET_P8_VECTOR)
+ if (!TARGET_POWER8)
+ return false;
+
+ if (!TARGET_ALTIVEC)
return false;
if (mode != V2DImode)
@@ -6795,7 +6794,7 @@ output_vec_const_move (rtx *operands)
else if (dest_vmx_p)
return "vspltisw %0,-1";
- else if (TARGET_P8_VECTOR)
+ else if (TARGET_POWER8 && TARGET_VSX)
return "xxlorc %x0,%x0,%x0";
else
@@ -7044,7 +7043,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
}
else
{
- if (TARGET_P8_VECTOR && TARGET_POWERPC64)
+ if (TARGET_POWER8 && TARGET_VSX && TARGET_POWERPC64)
{
rtx tmp_sf[4];
rtx tmp_si[4];
@@ -7649,7 +7648,7 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx
elt_rtx)
that future fusion opportunities can kick in, but must
generate VNOR elsewhere. */
rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
- rtx iorx = (TARGET_P8_VECTOR
+ rtx iorx = (TARGET_POWER8 && TARGET_ALTIVEC
? gen_rtx_IOR (V16QImode, notx, notx)
: gen_rtx_AND (V16QImode, notx, notx));
rtx tmp = gen_reg_rtx (V16QImode);
@@ -12771,7 +12770,7 @@ rs6000_secondary_reload_simple_move (enum
rs6000_reg_type to_type,
}
/* ISA 2.07: MTVSRWZ or MFVSRWZ. */
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8 && TARGET_VSX)
{
if (mode == SImode)
return true;
@@ -13532,7 +13531,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class
rclass)
VSPLTI<x>. */
if (value == -1)
{
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8 && TARGET_VSX)
return rclass;
else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
return ALTIVEC_REGS;
@@ -23640,7 +23639,7 @@ altivec_expand_vec_perm_le (rtx operands[4])
/* Invert the selector with a VNAND if available, else a VNOR.
The VNAND is preferred for future fusion opportunities. */
notx = gen_rtx_NOT (V16QImode, sel);
- iorx = (TARGET_P8_VECTOR
+ iorx = (TARGET_POWER8 && TARGET_ALTIVEC
? gen_rtx_IOR (V16QImode, notx, notx)
: gen_rtx_AND (V16QImode, notx, notx));
emit_insn (gen_rtx_SET (norreg, iorx));
@@ -23706,11 +23705,11 @@ altivec_expand_vec_perm_const (rtx target, rtx op0,
rtx op1,
BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct_v4si_be
: CODE_FOR_altivec_vmrghw_direct_v4si_le,
{8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}},
- {OPTION_MASK_P8_VECTOR,
+ {OPTION_MASK_VSX | OPTION_MASK_POWER8,
BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
: CODE_FOR_p8_vmrgow_v4sf_direct,
{0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27}},
- {OPTION_MASK_P8_VECTOR,
+ {OPTION_MASK_VSX | OPTION_MASK_POWER8,
BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
: CODE_FOR_p8_vmrgew_v4sf_direct,
{4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31}},
@@ -23818,7 +23817,7 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx
op1,
{
bool swapped;
- if ((patterns[j].mask & rs6000_isa_flags) == 0)
+ if ((patterns[j].mask & rs6000_isa_flags) != patterns[j].mask)
continue;
elt = patterns[j].perm[0];
@@ -24751,7 +24750,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "popcntd", OPTION_MASK_POPCNTD, false, true },
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
- { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 98952f11189..b3f3ac520ec 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -468,11 +468,11 @@ extern int rs6000_vector_align[];
#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
#define TARGET_MADDLD TARGET_MODULO
-/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
-#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
-#define TARGET_XSCVDPSPN TARGET_P8_VECTOR
-#define TARGET_XSCVSPDPN TARGET_P8_VECTOR
-#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
+#define TARGET_DIRECT_MOVE (TARGET_POWER8 && TARGET_VSX)
+#define TARGET_XSCVDPSPN (TARGET_POWER8 && TARGET_VSX)
+#define TARGET_XSCVSPDPN (TARGET_POWER8 && TARGET_VSX)
+#define TARGET_VADDUQM (TARGET_POWER8 && TARGET_ALTIVEC \
+ && TARGET_POWERPC64)
#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT)
#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 796aef1eb29..6bafb63b0b9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -401,7 +401,7 @@
(const_int 1)
(and (eq_attr "isa" "p8v")
- (match_test "TARGET_P8_VECTOR"))
+ (match_test "TARGET_POWER8 && TARGET_VSX"))
(const_int 1)
(and (eq_attr "isa" "p9")
@@ -868,7 +868,7 @@
;; D-form load to FPR register & move to Altivec register
;; Move Altivec register to FPR register and store
(define_mode_iterator ALTIVEC_DFORM [DF
- (SF "TARGET_P8_VECTOR")
+ (SF "TARGET_POWER8 && TARGET_VSX")
(DI "TARGET_POWERPC64")])
(include "darwin.md")
@@ -1272,7 +1272,7 @@
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(sign_extend:DI (match_operand:SI 1 "altivec_register_operand")))]
- "TARGET_P8_VECTOR && !TARGET_P9_VECTOR && reload_completed"
+ "TARGET_POWER8 && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx dest = operands[0];
@@ -6008,7 +6008,7 @@
operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8 && TARGET_VSX)
emit_insn (gen_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwax (operands[2], operands[1]));
@@ -6104,7 +6104,7 @@
operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_P8_VECTOR)
+ if (TARGET_POWER8 && TARGET_VSX)
emit_insn (gen_zero_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwzx (operands[2], operands[1]));
@@ -6518,7 +6518,8 @@
[(set (match_operand:QHSI 0 "memory_operand" "=Z")
(any_fix:QHSI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
(clobber (match_scratch:SI 2 "=wa"))]
- "(<QHSI:MODE>mode == SImode && TARGET_P8_VECTOR) || TARGET_P9_VECTOR"
+ "(<QHSI:MODE>mode == SImode && TARGET_POWER8 && TARGET_VSX)
+ || TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -6536,7 +6537,7 @@
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_FCTIWUZ && TARGET_STFIWX"
{
- if (!TARGET_P8_VECTOR)
+ if (!TARGET_POWER8 || !TARGET_VSX)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
@@ -7431,7 +7432,8 @@
(not:BOOL_128
(xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
(match_operand:BOOL_128 2 "vlogical_operand"))))]
- "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
+ "<MODE>mode == TImode || <MODE>mode == PTImode
+ || (TARGET_POWER8 && TARGET_ALTIVEC)"
"")
;; Rewrite nand into canonical form
@@ -7440,7 +7442,8 @@
(ior:BOOL_128
(not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand"))
(not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))]
- "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
+ "<MODE>mode == TImode || <MODE>mode == PTImode
+ || (TARGET_POWER8 && TARGET_ALTIVEC)"
"")
;; The canonical form is to have the negated element first, so we need to
@@ -7450,7 +7453,8 @@
(ior:BOOL_128
(not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))
(match_operand:BOOL_128 1 "vlogical_operand")))]
- "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
+ "<MODE>mode == TImode || <MODE>mode == PTImode
+ || (TARGET_POWER8 && TARGET_ALTIVEC)"
"")
;; 128-bit logical operations insns and split operations
@@ -7532,7 +7536,7 @@
[(not:BOOL_128
(match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
(match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
- "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
+ "(TARGET_POWER8 && TARGET_ALTIVEC) || (GET_CODE (operands[3]) == AND)"
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
return "xxl%q3 %x0,%x1,%x2";
@@ -7542,8 +7546,7 @@
return "#";
}
- "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
- && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
+ "&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
@@ -7569,9 +7572,9 @@
[(not:TI2
(match_operand:TI2 2 "int_reg_operand" "r,0,r"))
(match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
- "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
+ "!(TARGET_POWER8 && TARGET_ALTIVEC) && (GET_CODE (operands[3]) != AND)"
"#"
- "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
+ "&& reload_completed"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
@@ -7592,7 +7595,7 @@
(match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
(not:BOOL_128
(match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
- "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
+ "(TARGET_POWER8 && TARGET_ALTIVEC) || (GET_CODE (operands[3]) == AND)"
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
return "xxl%q3 %x0,%x1,%x2";
@@ -7602,8 +7605,7 @@
return "#";
}
- "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
- && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
+ "&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
@@ -7630,9 +7632,9 @@
(match_operand:TI2 1 "int_reg_operand" "r,0,r"))
(not:TI2
(match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
- "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
+ "!(TARGET_POWER8 && TARGET_ALTIVEC) && (GET_CODE (operands[3]) != AND)"
"#"
- "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
+ "&& reload_completed"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
@@ -7653,7 +7655,7 @@
(xor:BOOL_128
(match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
(match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
- "TARGET_P8_VECTOR"
+ "TARGET_POWER8 && TARGET_ALTIVEC"
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
return "xxleqv %x0,%x1,%x2";
@@ -7663,8 +7665,7 @@
return "#";
}
- "TARGET_P8_VECTOR && reload_completed
- && int_reg_operand (operands[0], <MODE>mode)"
+ "&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
rs6000_split_logical (operands, XOR, true, false, false);
@@ -7690,9 +7691,9 @@
(xor:TI2
(match_operand:TI2 1 "int_reg_operand" "r,0,r")
(match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
- "!TARGET_P8_VECTOR"
+ "!(TARGET_POWER8 && TARGET_ALTIVEC)"
"#"
- "reload_completed && !TARGET_P8_VECTOR"
+ "&& reload_completed"
[(const_int 0)]
{
rs6000_split_logical (operands, XOR, true, false, false);
@@ -10635,7 +10636,7 @@
(match_operand:SF 1 "any_operand"))
(set (match_operand:SF 2 "gpc_reg_operand")
(match_dup 0))]
- "!TARGET_P8_VECTOR
+ "!(TARGET_POWER8 && TARGET_VSX)
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 8632e106458..546e77592a1 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -487,7 +487,7 @@ Target Undocumented Mask(P8_FUSION_SIGN)
Var(rs6000_isa_flags)
Allow sign extension in fusion operations.
mpower8-vector
-Target Undocumented Mask(P8_VECTOR) Var(rs6000_isa_flags) WarnRemoved
+Target Undocumented WarnRemoved
Use vector and scalar instructions added in ISA 2.07.
mpower10-fusion
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 7a44a8a7e55..cf9f40e8f9f 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1035,7 +1035,7 @@
(define_expand "clz<mode>2"
[(set (match_operand:VEC_I 0 "register_operand")
(clz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
- "TARGET_P8_VECTOR")
+ "TARGET_POWER8 && TARGET_ALTIVEC")
;; Vector count trailing zeros
(define_expand "ctz<mode>2"
@@ -1047,7 +1047,7 @@
(define_expand "popcount<mode>2"
[(set (match_operand:VEC_I 0 "register_operand")
(popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))]
- "TARGET_P8_VECTOR")
+ "TARGET_POWER8 && TARGET_ALTIVEC")
;; Vector parity
(define_expand "parity<mode>2"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index dfb2485f2ec..2af29380c0a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1231,30 +1231,6 @@
[(set_attr "type" "vecperm")
(set_attr "length" "8")])
-(define_insn_and_split "*vspltisw_v2di_split"
- [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
- (match_operand:V2DI 1 "vspltisw_vupkhsw_constant_split" "W"))]
- "TARGET_P8_VECTOR && vspltisw_vupkhsw_constant_split (operands[1], V2DImode)"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- rtx op0 = operands[0];
- rtx op1 = operands[1];
- rtx tmp = can_create_pseudo_p ()
- ? gen_reg_rtx (V4SImode)
- : gen_lowpart (V4SImode, op0);
- int value;
-
- vspltisw_vupkhsw_constant_p (op1, V2DImode, &value);
- emit_insn (gen_altivec_vspltisw (tmp, GEN_INT (value)));
- emit_insn (gen_altivec_vupkhsw_direct (op0, tmp));
-
- DONE;
-}
- [(set_attr "type" "vecperm")
- (set_attr "length" "8")])
-
;; Prefer using vector registers over GPRs. Prefer using ISA 3.0's XXSPLTISB
;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
index 03e4bf0b31a..e2c59585f47 100644
--- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
@@ -28,7 +28,7 @@ vector signed int
test3 (vector signed int a, vector signed int b)
{
return vec_mergee (a, b);
- /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mcpu=power8'
and '-mvsx' options" "" { target *-*-* } .-1 } */
+ /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mcpu=power8'
and '-maltivec' options" "" { target *-*-* } .-1 } */
}
#pragma GCC target ("cpu=power6")
--
2.52.0
