AES, SHA and PCLMUL all depend on SSE2 (their *_SET masks pull it in),
but OPTION_MASK_ISA_SSE2_UNSET did not clear them. As a result,
-mno-sse (or -mno-sse2) left these ISAs enabled, together with
anything built on top of them such as VPCLMULQDQ, and the compiler
could then try to use patterns that require XMM registers when SSE
is not available.
Add AES, SHA and PCLMUL to the SSE2 unset mask so that disabling SSE2
also disables the ISAs that depend on it.
PR target/128105
gcc/ChangeLog:
* common/config/i386/i386-common.cc (OPTION_MASK_ISA_SSE2_UNSET):
Add OPTION_MASK_ISA_AES_UNSET, OPTION_MASK_ISA_SHA_UNSET and
OPTION_MASK_ISA_PCLMUL_UNSET.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr128105.c: New test.
Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index ed126f4c70d..4f61581ade7 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -222,7 +222,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_SSE_UNSET \
(OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
#define OPTION_MASK_ISA_SSE2_UNSET \
- (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
+ (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET \
+ | OPTION_MASK_ISA_AES_UNSET | OPTION_MASK_ISA_SHA_UNSET \
+ | OPTION_MASK_ISA_PCLMUL_UNSET)
#define OPTION_MASK_ISA_SSE3_UNSET \
(OPTION_MASK_ISA_SSE3 \
| OPTION_MASK_ISA_SSSE3_UNSET \
diff --git a/gcc/testsuite/gcc.target/i386/pr128105.c
b/gcc/testsuite/gcc.target/i386/pr128105.c
new file mode 100644
index 00000000000..9fba9bbc883
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr128105.c
@@ -0,0 +1,9 @@
+/* PR target/128105 */
+/* { dg-do compile } */
+/* { dg-options "-mvpclmulqdq -mno-sse" } */
+
+int
+foo (short s)
+{
+ return __builtin_crc16_data16 (0, s, 0);
+}
