On 09/09/2026 14:21, Karl Meakin wrote:
Port the following families of NEON intrinsics to the pragma-based
framework, and adds assembly tests for them:
* vcage
* vcagt
* vcale
* vcalt
* vceq
* vceqz
* vcge
* vcgez
* vcgt
* vcgtz
* vcle
* vclez
* vclt
* vcltz
* vtst
There is a slight regression in the
`vcage_f64.c`/`vcagt_f64.c`/`vcale_f64.c`/`vcalt_f64.c` tests:
I believe it is because `vcage_f64` now expands to GIMPLE rather than a call to
`__builtin_aarch64_fcage`, and then the conversion of a 0-or-1 bool to a
0-or-minus-1 bool is undone.
I think it is a minor regression, but I would be grateful if anyone has any
suggestions to fix it.
ChangeLog:
* V1: Initial revision.
* V2:
* Restore original definitions of the comparison functions in arm_fp16.h
rather than open-coding them
* Use `nonnegative_constant_operand` rather than `aarch64_nonnegative_vector_p` in
`aarch64_fac<optab><mode><vczle><vczbe>_const`
* V3:
* Rebase against master
* Add a FIXME to `facgt_constpool_1.c` to recognise more cases of
nonnegative arguments
* Add a FIXME to `vcage_f64.c` to use `FACGE` even when the result is a
0-or-1 bool rather than a 0-or-minus-1 bool
Karl Meakin (1):
aarch64: Port NEON comparison intrinsics to pragma-based framework
gcc/config/aarch64/aarch64-acle-builtins.h | 28 +
.../aarch64/aarch64-neon-builtins-base.cc | 80 +
.../aarch64/aarch64-neon-builtins-base.def | 154 +-
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64-simd.md | 22 +-
gcc/config/aarch64/aarch64.cc | 31 +
gcc/config/aarch64/arm_neon.h | 2111 +----------------
gcc/config/aarch64/predicates.md | 3 +
gcc/testsuite/gcc.target/aarch64/neon/vcage.c | 62 +
gcc/testsuite/gcc.target/aarch64/neon/vcagt.c | 62 +
gcc/testsuite/gcc.target/aarch64/neon/vcale.c | 62 +
gcc/testsuite/gcc.target/aarch64/neon/vcalt.c | 62 +
gcc/testsuite/gcc.target/aarch64/neon/vceq.c | 218 ++
gcc/testsuite/gcc.target/aarch64/neon/vceqz.c | 218 ++
gcc/testsuite/gcc.target/aarch64/neon/vcge.c | 190 ++
gcc/testsuite/gcc.target/aarch64/neon/vcgez.c | 126 +
gcc/testsuite/gcc.target/aarch64/neon/vcgt.c | 190 ++
gcc/testsuite/gcc.target/aarch64/neon/vcgtz.c | 126 +
gcc/testsuite/gcc.target/aarch64/neon/vcle.c | 190 ++
gcc/testsuite/gcc.target/aarch64/neon/vclez.c | 126 +
gcc/testsuite/gcc.target/aarch64/neon/vclt.c | 190 ++
gcc/testsuite/gcc.target/aarch64/neon/vcltz.c | 125 +
gcc/testsuite/gcc.target/aarch64/neon/vtst.c | 160 ++
.../aarch64/simd/facgt_constpool_1.c | 16 +-
.../gcc.target/aarch64/simd/vcage_f64.c | 5 +-
.../gcc.target/aarch64/simd/vcagt_f64.c | 2 +-
.../gcc.target/aarch64/simd/vcale_f64.c | 2 +-
.../gcc.target/aarch64/simd/vcalt_f64.c | 2 +-
28 files changed, 2456 insertions(+), 2108 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcage.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcagt.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcale.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcalt.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vceq.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vceqz.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcge.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcgez.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcgt.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcgtz.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcle.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vclez.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vclt.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vcltz.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vtst.c
Ping? I'd like to get this merged for stage 1
