On 11/11/26 3:15 PM, Matt Turner wrote:
Table 2-4 of the 21264/21364 Compiler Writer's Guide gives itof a
latency of 4, but ev6.md has used 3.
Measured on an EV68AL, itof and ftoi can only be chained through one
another, so I separated them by inserting a known number of FP adds. A
chain of itof, fadd, ftoi costs 13.105 cycles and itof, fadd, fadd, ftoi
costs 17.128, against 4 + 6 + 3 = 13 and 4 + 4 + 6 + 3 = 17 predicted by
the guide with an itof latency of 4.
An itof result consumed directly by an ftoi costs more than the two
latencies imply. A chain alternating the two takes 11.083 cycles per
round trip, and ftoi is 3, so the itof to ftoi edge is 8 rather than 4.
Routing the value through any FP operate removes the penalty, which is
why the chains above land on the latencies the guide predicts. Add a
bypass for the direct case.
Section 3.7.1 of the guide recommends ftoi and itof over bouncing a
value through memory, to avoid a store-load replay trap. With this
penalty the register path is only 1.20x faster than the memory path
(11.083 against 13.335 cycles).
gcc/ChangeLog:
* config/alpha/ev6.md (ev6_itof): Correct the latency to 4.
Add a bypass from ev6_itof to ev6_ftoi.
OK
jeff
