On Mon, Oct 22, 2012 at 5:25 PM, Alexander Ivchenko <aivch...@gmail.com> wrote:
> Please take a look at the updated patch. There is, thanks to Uros, changed
> expander and asm patterns.
>
> Considering H.J.'s comments:
>
> 1) Yes, I added new option -mxsaveopt
> 2) No.The FXSAVE and FXRSTOR instructions are not considered part of the SSE
> instruction group.
> 3) Done.
> 4) Fixed.
> 5) I'm not sure, there was already BIT_FXSAVE in cpuid.h, that had been
> using in
> /libgcc/config/i386/crtfastmath.c. I didn't change that. May be it would
> be enough to
> change the option name from -mfxsave to -mfxsr?
> 6) Not sure about the list of all processors, that support those features. I
> added to those I know support them.
> 7) Done.
Restore-type insns do not store to memory, but read memory, so they
should be defined like:
[(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
UNSPECV_FXRSTOR)]
Where save-type insn should look like:
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec_volatile:BLK [(const_int 0)] UNSPECV_FXSAVE)]
When they also read additional registers:
[(unspec_volatile:BLK
[(match_operand:BLK 0 "memory_operand" "m")
(match_operand:SI 1 "register_operand" "a")
(match_operand:SI 2 "register_operand" "d")]
UNSPECV_XRSTOR)]
and
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec_volatile:BLK
[(match_operand:SI 1 "register_operand" "a")
(match_operand:SI 2 "register_operand" "d")]
UNSPECV_XSAVE)]
(And in similar way a 32bit patterns with DImode operand).
I missed this detail in my previous review.
BTW: BLKmode is a bit unusual, so I hope these patterns work as expected.
Also, please do not use "mem" and "mask" in the headers; use "__P" and
"__M" for "pointer" and "mask", as is the case in other headers.
Uros.
