[AArch64] __atomic_thread_fence and release memory model

[Yvan Roux]

Hi,

a call to the builtin __atomic_thread_fence with the memory model
__ATOMIC_RELEASE generates a data memory barrier with the option ish
whereas I think that the one which has the "release" semantic is ishst
(store before store). The attached patch implements my proposal.

Thanks,
Yvan

--
gcc/

2013-02-14  Yvan Roux  <yvan.r...@linaro.org>

        * config/aarch64/atomics.md (dmb): Emit release mode barrier.

0001-AArch64-fix-data-memory-barrier-release-mode.patch
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