Oops, I missed that the release semantics is not just store before store but also load before store, sorry for that :(
Yvan On 14 February 2013 16:40, Yvan Roux <yvan.r...@linaro.org> wrote: > Hi, > > a call to the builtin __atomic_thread_fence with the memory model > __ATOMIC_RELEASE generates a data memory barrier with the option ish > whereas I think that the one which has the "release" semantic is ishst > (store before store). The attached patch implements my proposal. > > Thanks, > Yvan > > -- > gcc/ > > 2013-02-14 Yvan Roux <yvan.r...@linaro.org> > > * config/aarch64/atomics.md (dmb): Emit release mode barrier.
