On 27 June 2014 14:55, Ramana Radhakrishnan <ramana....@googlemail.com> wrote:
> On Thu, Jun 5, 2014 at 11:04 PM, Christophe Lyon
> <christophe.l...@linaro.org> wrote:
>> vadd tests also show how to add directives to scan the assembly
>> output.
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_op.inc
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_op.inc
>> new file mode 100644
>> index 0000000..3483e0e
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/binary_op.inc
>> @@ -0,0 +1,70 @@
>> +/* Template file for binary operator validation.
>> +
>> + This file is meant to be included by the relevant test files, which
>> + have to define the intrinsic family to test. If a given intrinsic
>> + supports variants which are not supported by all the other binary
>> + operators, these can be tested by providing a definition for
>> + EXTRA_TESTS. */
>> +
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +void FNNAME (INSN_NAME) (void)
>> +{
>> + /* Basic test: y=OP(x1,x2), then store the result. */
>> +#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
>> + VECT_VAR(vector_res, T1, W, N) = \
>> + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
>> + VECT_VAR(vector2, T1, W, N)); \
>> + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W,
>> N))
>> +
>> +#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N) \
>> + TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
>> +
>> + DECL_VARIABLE_ALL_VARIANTS(vector);
>> + DECL_VARIABLE_ALL_VARIANTS(vector2);
>> + DECL_VARIABLE_ALL_VARIANTS(vector_res);
>> +
>> + clean_results ();
>> +
>> + /* Initialize input "vector" from "buffer". */
>> + TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
>> +
>> + /* Fill input vector2 with arbitrary values. */
>> + VDUP(vector2, , int, s, 8, 8, 2);
>> + VDUP(vector2, , int, s, 16, 4, -4);
>> + VDUP(vector2, , int, s, 32, 2, 3);
>> + VDUP(vector2, , int, s, 64, 1, 100);
>> + VDUP(vector2, , uint, u, 8, 8, 20);
>> + VDUP(vector2, , uint, u, 16, 4, 30);
>> + VDUP(vector2, , uint, u, 32, 2, 40);
>> + VDUP(vector2, , uint, u, 64, 1, 2);
>> + VDUP(vector2, q, int, s, 8, 16, -10);
>> + VDUP(vector2, q, int, s, 16, 8, -20);
>> + VDUP(vector2, q, int, s, 32, 4, -30);
>> + VDUP(vector2, q, int, s, 64, 2, 24);
>> + VDUP(vector2, q, uint, u, 8, 16, 12);
>> + VDUP(vector2, q, uint, u, 16, 8, 3);
>> + VDUP(vector2, q, uint, u, 32, 4, 55);
>> + VDUP(vector2, q, uint, u, 64, 2, 3);
>> +
>> + /* Apply a binary operator named INSN_NAME. */
>> + TEST_MACRO_ALL_VARIANTS_1_5(TEST_BINARY_OP, INSN_NAME);
>> +
>> + CHECK_RESULTS (TEST_MSG, "");
>> +
>> +#ifdef EXTRA_TESTS
>> + EXTRA_TESTS();
>> +#endif
>> +}
>> +
>> +int main (void)
>> +{
>> + FNNAME (INSN_NAME) ();
>> +
>> + return 0;
>> +}
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vadd.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vadd.c
>> new file mode 100644
>> index 0000000..64edc3f
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vadd.c
>> @@ -0,0 +1,109 @@
>> +#define INSN_NAME vadd
>> +#define TEST_MSG "VADD/VADDQ"
>> +
>> +/* Extra tests for functions requiring floating-point types. */
>> +void exec_vadd_f32(void);
>> +#define EXTRA_TESTS exec_vadd_f32
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf2, 0xf3, 0xf4, 0xf5,
>> + 0xf6, 0xf7, 0xf8, 0xf9 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffec, 0xffed, 0xffee, 0xffef };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff3, 0xfffffff4 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x54 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x5, 0x6, 0x7,
>> + 0x8, 0x9, 0xa, 0xb };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xe, 0xf, 0x10, 0x11 };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x18, 0x19 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xe6, 0xe7, 0xe8, 0xe9,
>> + 0xea, 0xeb, 0xec, 0xed,
>> + 0xee, 0xef, 0xf0, 0xf1,
>> + 0xf2, 0xf3, 0xf4, 0xf5 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xffdc, 0xffdd, 0xffde, 0xffdf,
>> + 0xffe0, 0xffe1, 0xffe2, 0xffe3 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffd2, 0xffffffd3,
>> + 0xffffffd4, 0xffffffd5 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x8, 0x9 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xfc, 0xfd, 0xfe, 0xff,
>> + 0x0, 0x1, 0x2, 0x3,
>> + 0x4, 0x5, 0x6, 0x7,
>> + 0x8, 0x9, 0xa, 0xb };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff3, 0xfff4, 0xfff5, 0xfff6,
>> + 0xfff7, 0xfff8, 0xfff9, 0xfffa };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x27, 0x28, 0x29, 0x2a };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3,
>> + 0xfffffffffffffff4 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>> +/* Expected results for float32 variants. Needs to be separated since
>> + the generic test function does not test floating-point
>> + versions. */
>> +VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40d9999a, 0x40d9999a };
>> +VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x41100000, 0x41100000,
>> + 0x41100000, 0x41100000 };
>> +
>> +void exec_vadd_f32(void)
>> +{
>> + DECL_VARIABLE(vector, float, 32, 2);
>> + DECL_VARIABLE(vector, float, 32, 4);
>> +
>> + DECL_VARIABLE(vector2, float, 32, 2);
>> + DECL_VARIABLE(vector2, float, 32, 4);
>> +
>> + DECL_VARIABLE(vector_res, float, 32, 2);
>> + DECL_VARIABLE(vector_res, float, 32, 4);
>> +
>> + VDUP(vector, , float, f, 32, 2, 2.3f);
>> + VDUP(vector, q, float, f, 32, 4, 3.4f);
>> +
>> + VDUP(vector2, , float, f, 32, 2, 4.5f);
>> + VDUP(vector2, q, float, f, 32, 4, 5.6f);
>> +
>> + TEST_BINARY_OP(INSN_NAME, , float, f, 32, 2);
>> + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
>> +
>> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
>> + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
>> +}
>> +
>> +/* { dg-final { scan-assembler-times "vadd\.i8\[ \]+\[dD\]\[0-9\]+,
>> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.i16\[ \]+\[dD\]\[0-9\]+,
>> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.i32\[ \]+\[dD\]\[0-9\]+,
>> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.i64\[ \]+\[dD\]\[0-9\]+,
>> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +
>> +/* { dg-final { scan-assembler-times "vadd\.i8\[ \]+\[qQ\]\[0-9\]+,
>> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.i16\[ \]+\[qQ\]\[0-9\]+,
>> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.i32\[ \]+\[qQ\]\[0-9\]+,
>> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.i64\[ \]+\[qQ\]\[0-9\]+,
>> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 { target arm*-*-*-* } } } */
>> +
>> +/* { dg-final { scan-assembler-times "vadd\.f32\[ \]+\[dD\]\[0-9\]+,
>> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 1 { target arm*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "vadd\.f32\[ \]+\[qQ\]\[0-9\]+,
>> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 1 { target arm*-*-*-* } } } */
>> +
>> +
>> +
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.8\[bB\], \[vV\]\[0-9\]+.8\[bB\], \[vV\]\[0-9\]+.8\[bB\]" 2
>> { target aarch64*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.4\[hH\], \[vV\]\[0-9\]+.4\[hH\], \[vV\]\[0-9\]+.4\[hH\]" 2
>> { target aarch64*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.2\[sS\], \[vV\]\[0-9\]+.2\[sS\], \[vV\]\[0-9\]+.2\[sS\]" 2
>> { target aarch64*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[xX\]\[0-9\]+, \[xX\]\[0-9\]+, \[xX\]\[0-9\]+" 2 { target aarch64*-*-*-*
>> } } } */
>> +
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.16\[bB\], \[vV\]\[0-9\]+.16\[bB\],
>> \[vV\]\[0-9\]+.16\[bB\]" 2 { target aarch64*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.8\[hH\], \[vV\]\[0-9\]+.8\[hH\], \[vV\]\[0-9\]+.8\[hH\]" 2
>> { target aarch64*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.4\[sS\], \[vV\]\[0-9\]+.4\[sS\], \[vV\]\[0-9\]+.4\[sS\]" 2
>> { target aarch64*-*-*-* } } } */
>> +/* { dg-final { scan-assembler-times "\[ \]add\[
>> \]+\[vV\]\[0-9\]+.2\[dD\], \[vV\]\[0-9\]+.2\[dD\], \[vV\]\[0-9\]+.2\[dD\]" 2
>> { target aarch64*-*-*-* } } } */
>> +
>> +/* { dg-final { scan-assembler-times "fadd\[ \]+\[vV\]\[0-9\]+.2\[sS\],
>> \[vV\]\[0-9\]+.2\[sS\], \[vV\]\[0-9\]+.2\[sS\]" 1 { target aarch64*-*-*-* }
>> } } */
>> +/* { dg-final { scan-assembler-times "fadd\[ \]+\[vV\]\[0-9\]+.4\[sS\],
>> \[vV\]\[0-9\]+.4\[sS\], \[vV\]\[0-9\]+.4\[sS\]" 1 { target aarch64*-*-*-* }
>> } } */
>
> I'd rather drop the scan-assembler. I'm not convinced that the fragile
> nature of this is required. Can you add a note to the README that says
> that this is meant to be a complete execution test for the Advanced
> SIMD intrinsics and does not cover all the assembler that is
Sure.
> generated. If we have issues and regressions, we add specific directed
> tests rather than carrying more noise as you've just mentioned. Any
> thoughts ?
I'm not sure if it's going to be really fragile. But for sure it will
be difficult to read if it happens that we have to conditionalize the
scan-asm depending on the optim level (e.g. if the compiler prefers to
use core registers at some optimization levels).
OTOH, adding such tests systematically now is probably easier than
waiting for a bug report and then adding a new test that wouldn't
cover all the variants.
Maybe we can drop the scan-asm directives for now, add all the
existing tests, and as a 2nd pass add scan-asm directives. It could be
easier to review and introduce less PRs at once :-)
So if you are happy with the whole series, I could:
- update the README so say it's execution-only at least for the time being
- remove scan-asm from vadd.c
- commit the series I've posted so far
- continue the conversion
- push & hopefully commit all the tests I have so far
- have a 2nd pass on all the tests and add scan-asm directives,
checking what kind of problems it raises
- possibly add tests for ACLE (would be in another directory)
- add missing aarch32 intrinsics if any
- add missing aarch64 intrinsics
What do you think?
Thanks,
Christophe.
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vand.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vand.c
>> new file mode 100644
>> index 0000000..e7e65dd
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vand.c
>> @@ -0,0 +1,45 @@
>> +#define INSN_NAME vand
>> +#define TEST_MSG "VAND/VANDQ"
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x0, 0x0, 0x2, 0x2,
>> + 0x0, 0x0, 0x2, 0x2 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x0, 0x1 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x60 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x10, 0x10, 0x10, 0x10,
>> + 0x14, 0x14, 0x14, 0x14 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10, 0x10, 0x12, 0x12 };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x20, 0x20 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x0 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf0, 0xf2, 0xf2,
>> + 0xf4, 0xf4, 0xf6, 0xf6,
>> + 0xf0, 0xf0, 0xf2, 0xf2,
>> + 0xf4, 0xf4, 0xf6, 0xf6 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe0, 0xffe0, 0xffe0, 0xffe0,
>> + 0xffe4, 0xffe4, 0xffe4, 0xffe4 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffe0, 0xffffffe0,
>> + 0xffffffe2, 0xffffffe2 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x10, 0x10 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
>> + 0x4, 0x4, 0x4, 0x4,
>> + 0x8, 0x8, 0x8, 0x8,
>> + 0xc, 0xc, 0xc, 0xc };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x0, 0x1, 0x2, 0x3,
>> + 0x0, 0x1, 0x2, 0x3 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x30, 0x31, 0x32, 0x33 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x1 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vbic.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vbic.c
>> new file mode 100644
>> index 0000000..83e57ff
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vbic.c
>> @@ -0,0 +1,46 @@
>> +#define INSN_NAME vbic
>> +#define TEST_MSG "VBIC/VBICQ"
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf4, 0xf5, 0xf4, 0xf5 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x0, 0x1, 0x2, 0x3 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffff90 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe0, 0xe1, 0xe2, 0xe3,
>> + 0xe0, 0xe1, 0xe2, 0xe3 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe0, 0xffe1, 0xffe0, 0xffe1 };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffd0, 0xffffffd1 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x0, 0x1, 0x0, 0x1,
>> + 0x0, 0x1, 0x0, 0x1,
>> + 0x8, 0x9, 0x8, 0x9,
>> + 0x8, 0x9, 0x8, 0x9 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0x11, 0x12, 0x13,
>> + 0x10, 0x11, 0x12, 0x13 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0x11, 0x10, 0x11 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffe0,
>> 0xffffffffffffffe1 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
>> + 0xfff4, 0xfff4, 0xfff4, 0xfff4 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffc0, 0xffffffc0,
>> + 0xffffffc0, 0xffffffc0 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
>> + 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/veor.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/veor.c
>> new file mode 100644
>> index 0000000..474b225
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/veor.c
>> @@ -0,0 +1,47 @@
>> +#define INSN_NAME veor
>> +#define TEST_MSG "VEOR/VEORQ"
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf2, 0xf3, 0xf0, 0xf1,
>> + 0xf6, 0xf7, 0xf4, 0xf5 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xc, 0xd, 0xe, 0xf };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff3, 0xfffffff2 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffff94 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe4, 0xe5, 0xe6, 0xe7,
>> + 0xe0, 0xe1, 0xe2, 0xe3 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffee, 0xffef, 0xffec, 0xffed };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffd8, 0xffffffd9 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x6, 0x7, 0x4, 0x5,
>> + 0x2, 0x3, 0x0, 0x1,
>> + 0xe, 0xf, 0xc, 0xd,
>> + 0xa, 0xb, 0x8, 0x9 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c, 0x1d, 0x1e, 0x1f,
>> + 0x18, 0x19, 0x1a, 0x1b };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x12, 0x13, 0x10, 0x11 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffe8,
>> + 0xffffffffffffffe9 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xfc, 0xfd, 0xfe, 0xff,
>> + 0xf8, 0xf9, 0xfa, 0xfb,
>> + 0xf4, 0xf5, 0xf6, 0xf7,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0,
>> + 0xfff7, 0xfff6, 0xfff5, 0xfff4 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffc7, 0xffffffc6,
>> + 0xffffffc5, 0xffffffc4 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3,
>> + 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vorn.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vorn.c
>> new file mode 100644
>> index 0000000..6905cb6
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vorn.c
>> @@ -0,0 +1,48 @@
>> +#define INSN_NAME vorn
>> +#define TEST_MSG "VORN/VORNQ"
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xfd, 0xfd, 0xff, 0xff,
>> + 0xfd, 0xfd, 0xff, 0xff };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffd };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffffb };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfb, 0xfb, 0xfb, 0xfb,
>> + 0xff, 0xff, 0xff, 0xff };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff3, 0xfff3 };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff7, 0xfffffff7 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffffd };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf9, 0xf9, 0xfb, 0xfb,
>> + 0xfd, 0xfd, 0xff, 0xff,
>> + 0xf9, 0xf9, 0xfb, 0xfb,
>> + 0xfd, 0xfd, 0xff, 0xff };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
>> + 0xfff7, 0xfff7, 0xfff7, 0xfff7 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffd, 0xfffffffd,
>> + 0xffffffff, 0xffffffff };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff7,
>> + 0xfffffffffffffff7 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
>> + 0xf7, 0xf7, 0xf7, 0xf7,
>> + 0xfb, 0xfb, 0xfb, 0xfb,
>> + 0xff, 0xff, 0xff, 0xff };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffc, 0xfffd, 0xfffe, 0xffff,
>> + 0xfffc, 0xfffd, 0xfffe, 0xffff };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff8, 0xfffffff9,
>> + 0xfffffffa, 0xfffffffb };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffffc,
>> + 0xfffffffffffffffd };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vorr.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vorr.c
>> new file mode 100644
>> index 0000000..b2a7dff
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vorr.c
>> @@ -0,0 +1,48 @@
>> +#define INSN_NAME vorr
>> +#define TEST_MSG "VORR/VORRQ"
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf2, 0xf3, 0xf2, 0xf3,
>> + 0xf6, 0xf7, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfffc, 0xfffd, 0xfffe, 0xffff };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff3, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff4 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf4, 0xf5, 0xf6, 0xf7,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfffe, 0xffff, 0xfffe, 0xffff };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff8, 0xfffffff9 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf6, 0xf7, 0xf6, 0xf7,
>> + 0xf6, 0xf7, 0xf6, 0xf7,
>> + 0xfe, 0xff, 0xfe, 0xff,
>> + 0xfe, 0xff, 0xfe, 0xff };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffc, 0xfffd, 0xfffe, 0xffff,
>> + 0xfffc, 0xfffd, 0xfffe, 0xffff };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff2, 0xfffffff3,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff8,
>> + 0xfffffffffffffff9 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xfc, 0xfd, 0xfe, 0xff,
>> + 0xfc, 0xfd, 0xfe, 0xff,
>> + 0xfc, 0xfd, 0xfe, 0xff,
>> + 0xfc, 0xfd, 0xfe, 0xff };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
>> + 0xfff7, 0xfff7, 0xfff7, 0xfff7 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff7, 0xfffffff7,
>> + 0xfffffff7, 0xfffffff7 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3,
>> + 0xfffffffffffffff3 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> diff --git a/gcc/testsuite/gcc.target/arm/neon-intrinsics/vsub.c
>> b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vsub.c
>> new file mode 100644
>> index 0000000..7620479
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/neon-intrinsics/vsub.c
>> @@ -0,0 +1,82 @@
>> +#define INSN_NAME vsub
>> +#define TEST_MSG "VSUB/VSUBQ"
>> +
>> +/* Extra tests for functions requiring floating-point types */
>> +void exec_vsub_f32(void);
>> +#define EXTRA_TESTS exec_vsub_f32
>> +
>> +#include "binary_op.inc"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xee, 0xef, 0xf0, 0xf1,
>> + 0xf2, 0xf3, 0xf4, 0xf5 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffed, 0xffffffee };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffff8c };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xdc, 0xdd, 0xde, 0xdf,
>> + 0xe0, 0xe1, 0xe2, 0xe3 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffd2, 0xffd3, 0xffd4, 0xffd5 };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffc8, 0xffffffc9 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffffee };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xfa, 0xfb, 0xfc, 0xfd,
>> + 0xfe, 0xff, 0x0, 0x1,
>> + 0x2, 0x3, 0x4, 0x5,
>> + 0x6, 0x7, 0x8, 0x9 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x4, 0x5, 0x6, 0x7,
>> + 0x8, 0x9, 0xa, 0xb };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xe, 0xf, 0x10, 0x11 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffd8,
>> + 0xffffffffffffffd9 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xe4, 0xe5, 0xe6, 0xe7,
>> + 0xe8, 0xe9, 0xea, 0xeb,
>> + 0xec, 0xed, 0xee, 0xef,
>> + 0xf0, 0xf1, 0xf2, 0xf3};
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffed, 0xffee, 0xffef, 0xfff0,
>> + 0xfff1, 0xfff2, 0xfff3, 0xfff4 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffb9, 0xffffffba,
>> + 0xffffffbb, 0xffffffbc };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffed,
>> + 0xffffffffffffffee };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>> +/* Expected results for float32 variants. Needs to be separated since
>> + the generic test function does not test floating-point
>> + versions. */
>> +VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc00ccccd, 0xc00ccccd };
>> +VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc00ccccc, 0xc00ccccc,
>> + 0xc00ccccc, 0xc00ccccc };
>> +
>> +void exec_vsub_f32(void)
>> +{
>> + DECL_VARIABLE(vector, float, 32, 2);
>> + DECL_VARIABLE(vector, float, 32, 4);
>> +
>> + DECL_VARIABLE(vector2, float, 32, 2);
>> + DECL_VARIABLE(vector2, float, 32, 4);
>> +
>> + DECL_VARIABLE(vector_res, float, 32, 2);
>> + DECL_VARIABLE(vector_res, float, 32, 4);
>> +
>> + VDUP(vector, , float, f, 32, 2, 2.3f);
>> + VDUP(vector, q, float, f, 32, 4, 3.4f);
>> +
>> + VDUP(vector2, , float, f, 32, 2, 4.5f);
>> + VDUP(vector2, q, float, f, 32, 4, 5.6f);
>> +
>> + TEST_BINARY_OP(INSN_NAME, , float, f, 32, 2);
>> + TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
>> +
>> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
>> + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
>> +}
>> --
>> 1.8.3.2
>
>
> Otherwise OK (modulo any rebasing issue / anything we may decide on
> moving this into gcc.target/aarch64).
>
OK thanks.
