Hi all, we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to revision 212419 as r212661. We have also backported this set of revisions:
r209794 as r212697 : PR c/60114 r209797 as r212675 : [ARM] Wrap long literals in HOST_WIDE_INT_C in aarch-common.c r209858 as r212697 : [ARM/AArch64] Use signed chars in gcc.dg/pr60114.c. r209940 as r212665 : Add execution + assembler tests of AArch64 UZP Intrinsics. r209943 as r212665 : Rewrite AArch64 UZP Intrinsics using __builtin_shuffle. r209947 as r212665 : Add execution tests of ARM UZP Intrinsics. r210148 as r212698 : Add execution + assembler tests of AArch64 TRN Intrinsics. r210151 as r212698 : Reimplement AArch64 TRN intrinsics with __builtin_shuffle. r210152 as r212677 : Add execution + assembler tests of AArch64 EXT intrinsics. r210153 as r212715 : Add execution + assembler tests of AArch64 REV Neon Intrinsics. r210216 as r212714 : Neon intrinsics TLC - Replace intrinsics with GNU C implementations. r210218 as r212714 : Neon intrinsics TLC - remove dead code. r210219 as r212714 : Neon intrinsics TLC - remove ML r210355 as r212669 : Implement HARD_REGNO_CALLER_SAVE_MODE for AArch64 r210369 as r212678 : [ARM] Remove vzip, vuzp, vtrn builtins and cleanup r210422 as r212698 : Add execution tests of ARM TRN Intrinsics. r210471 as r212679 : [ARM][cleanup] Use enum name instead of integer value for PARAM_SCHED_PRESSURE_ALGORITHM. r210828 as r212672 : TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64 r210861 as r212695 : [AARCH64] Support tail indirect function call. r210967 as r212680 : [ARM] Vectorise bswap* in aarch32. r210996 as r212681 : [AArch64] Fix stack protector for ILP32 r211050 as r212682 : [AArch32] Fix PR/61331 r211058 as r212677 : Detect EXT patterns to vec_perm_const, use for EXT intrinsics r211059 as r212677 : Add execution tests of ARM EXT intrinsics r211073 as r212683 : [ARM] Use mov_imm type for movw operations consistently r211103 as r212672 : TARGET_ATOMIC_ASSIGN_EXPAND_FENV ARM r211129 as r212685 : Fix PR target/61154 r211148 as r212673 : ILP32 dynamic linker r211174 as r212715 : Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics. r211177 as r212677 : Detect EXT patterns to vec_perm_const, use for EXT intrinsics. r211185 as r212690 : [PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.h r211186 as r212690 : AArch64 2/2] Correct signedness of builtins, remove casts from arm_neon.h r211268 as r212686 : [AArch64] clarify stack layout diagram r211314 as r212691 : [AArch64] Implement movmem for the benefit of inline memcpy r211371 as r212687 : Remove XFmode from ARM backend. r211408 as r212689 : [AArch64] Fix REG_CFA_RESTORE mode. r211416 as r212689 : [AArch64] Fix layout of frame layout code. r211418 as r212688 : [AArch64] Fix some reg-to-reg move scheduler types. r211440 as r212720 : [AArch64] Implement CRC32 ACLE intrinsics r211441 as r212720 : [AArch64] Add CRC32 ACLE intrinsics testsuite. r211771 as r212696 : [genattrtab] Fix memory corruption, allocate enough memory for all bypassed reservations r211887 as r212722 : [AArch64] Implement ADD in vector registers for 32-bit scalar values. r211899 as r212722 : [AArch64] Implement ADD in vector registers for 32-bit scalar values. This will be part of our 2014.07 release. Thanks, Yvan
