This patch fixes a bug in aarch64_register_move_cost(): GET_MODE_SIZE is in
bytes not bits. As a
result the FP2FP cost doesn't need to be set to 4 to catch the special case for
Q register moves.
ChangeLog:
2014-09-04 Wilco Dijkstra <wdijk...@arm.com>
* gcc/config/aarch64/aarch64.c (aarch64_register_move_cost):
Fix Q register handling. Set FP2FP move cost.
---
gcc/config/aarch64/aarch64.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 6245f59..57bb083 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -219,10 +219,7 @@ static const struct cpu_regmove_cost generic_regmove_cost =
NAMED_PARAM (GP2GP, 1),
NAMED_PARAM (GP2FP, 2),
NAMED_PARAM (FP2GP, 2),
- /* We currently do not provide direct support for TFmode Q->Q move.
- Therefore we need to raise the cost above 2 in order to have
- reload handle the situation. */
- NAMED_PARAM (FP2FP, 4)
+ NAMED_PARAM (FP2FP, 2)
};
/* Generic costs for vector insn classes. */
@@ -5846,7 +5843,7 @@ aarch64_register_move_cost (enum machine_mode mode,
secondary reload. A general register is used as a scratch to move
the upper DI value and the lower DI value is moved directly,
hence the cost is the sum of three moves. */
- if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)
+ if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16)
return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
return regmove_cost->FP2FP;
--
1.9.1
