Patch attached for commit as I don't have write access.
ChangeLog:
2014-09-11 Wilco Dijkstra <wdijk...@arm.com>
* gcc/config/aarch64/aarch64.c (aarch64_register_move_cost):
Fix Q register move handling. (generic_regmove_cost): Undo raised
FP2FP move cost as Q register moves are now handled correctly.
> -----Original Message-----
> From: Marcus Shawcroft [mailto:marcus.shawcr...@gmail.com]
> Sent: 04 September 2014 16:54
> To: Wilco Dijkstra
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 2/4] AArch64: Fix cost for Q register moves
>
> On 4 September 2014 16:41, Wilco Dijkstra <wdijk...@arm.com> wrote:
> >> From: Marcus Shawcroft [mailto:marcus.shawcr...@gmail.com]
> >> > - NAMED_PARAM (FP2FP, 4)
> >> > + NAMED_PARAM (FP2FP, 2)
> >>
> >> This is not directly related to the change below and it is missing
> >> from the ChangeLog. Originally this number had to be > 2 in order
> >> for secondary reload to kick in. See the comment above the second
> >> hunk of this patch. Why is it OK to lower this number ?
> >
> > It is related because the GET_MODE_SIZE bug means it never returns the
> > correct cost, but instead returns the FP2FP cost. So the FP2FP cost had
> > to be artificially increased. With the fix this is no longer required.
>
> Yep, I read the code again, I understand. You still need to fix the
> ChangeLog. OK to commit with a fixed ChangeLog.
>
> Cheers
>
> /Marcus
---
gcc/config/aarch64/aarch64.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 56b8eda..62b0168 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -215,10 +215,7 @@ static const struct cpu_regmove_cost generic_regmove_cost =
NAMED_PARAM (GP2GP, 1),
NAMED_PARAM (GP2FP, 2),
NAMED_PARAM (FP2GP, 2),
- /* We currently do not provide direct support for TFmode Q->Q move.
- Therefore we need to raise the cost above 2 in order to have
- reload handle the situation. */
- NAMED_PARAM (FP2FP, 4)
+ NAMED_PARAM (FP2FP, 2)
};
/* Generic costs for vector insn classes. */
@@ -5961,7 +5958,7 @@ aarch64_register_move_cost (enum machine_mode mode,
secondary reload. A general register is used as a scratch to move
the upper DI value and the lower DI value is moved directly,
hence the cost is the sum of three moves. */
- if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)
+ if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16)
return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
return regmove_cost->FP2FP;
--
1.9.1
