The following patch-series adds optimized support for the APM X-Gene 1 by providing a cost-model and pipeline-model. The pipeline-model has a few long reservation-chains, but looking at the stats for the generated NDA shows that it's well below other AArch64 cores (e.g. Cortex-A53) in overall size.
This includes all the requested enhancements and cleans up the naming of the various states and reservations in 'xgene1.md'. Even though it isn't wired into the 32bit ARM backend yet, we've decided to keep the machine-description in config/arm... after all, the X-Gene family is backwards compatible with ARMv7 and our benchmarking has shown good potential for performance improvements from improving the instruction selection and scheduling when using ARMv7 code (after all, X-Gene 1 is a 4-way superscalar design). After having a few further discussions with my colleagues regarding the latencies and modelling of divides in the pipeline, we've readjusted the modelling of the divides another time... even though it doesn't make a difference in real-world benchmarks. Thanks to everyone who took the time to review and comment. Philipp Tomsich (2): Core definition for APM XGene-1 and associated cost-table. Pipeline model for APM XGene-1. gcc/ChangeLog | 14 + gcc/config/aarch64/aarch64-cores.def | 1 + gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.c | 62 ++++ gcc/config/aarch64/aarch64.md | 3 +- gcc/config/arm/aarch-cost-tables.h | 101 +++++++ gcc/config/arm/xgene1.md | 532 +++++++++++++++++++++++++++++++++++ gcc/doc/invoke.texi | 3 +- 8 files changed, 715 insertions(+), 3 deletions(-) create mode 100644 gcc/config/arm/xgene1.md -- 1.9.1
