This splits the addic patterns from the add/addi patterns, and merges the
insns and splitters.
Also change type "compare" to "add" for "addic." (the dot form).
2014-12-08 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
PR target/64180
* config/rs6000/rs6000.md (*add<mode>3_internal1): Rename to
"*add<mode>3".
(*add<mode>3_internal2, *add<mode>3_internal3, and (their splitters):
Delete.
(*add<mode>3_dot, *add<mode>3_dot2): New.
(*add<mode>3_imm_dot, *add<mode>3_imm_dot2): New.
---
gcc/config/rs6000/rs6000.md | 119 +++++++++++++++++++++++++++-----------------
1 file changed, 74 insertions(+), 45 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1647f8b..dcdb7c1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1491,7 +1491,7 @@ (define_expand "add<mode>3"
}
})
-(define_insn "*add<mode>3_internal1"
+(define_insn "*add<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r")
(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b")
(match_operand:GPR 2 "add_operand" "r,I,L")))]
@@ -1510,70 +1510,99 @@ (define_insn "addsi3_high"
"addis %0,%1,ha16(%2)"
[(set_attr "type" "add")])
-(define_insn "*add<mode>3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:P 2 "reg_or_short_operand"
"r,I,r,I"))
+(define_insn_and_split "*add<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:P 3 "=r,r,r,r"))]
- ""
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "<MODE>mode == Pmode"
"@
- add. %3,%1,%2
- addic. %3,%1,%2
- #
+ add. %0,%1,%2
#"
- [(set_attr "type" "add,compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (plus:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "add")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,8,8")])
+ (set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "reg_or_short_operand" ""))
+(define_insn_and_split "*add<mode>3_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:GPR 3 ""))]
- "reload_completed"
- [(set (match_dup 3)
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(plus:GPR (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
+ (match_dup 2)))]
+ "<MODE>mode == Pmode"
+ "@
+ add. %0,%1,%2
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (plus:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
-(define_insn "*add<mode>3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:P 2 "reg_or_short_operand"
"r,I,r,I"))
+(define_insn_and_split "*add<mode>3_imm_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "short_cint_operand" "I,I"))
(const_int 0)))
- (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
- (plus:P (match_dup 1)
- (match_dup 2)))]
- ""
+ (clobber (match_scratch:GPR 0 "=r,r"))
+ (clobber (reg:GPR CA_REGNO))]
+ "<MODE>mode == Pmode"
"@
- add. %0,%1,%2
addic. %0,%1,%2
- #
#"
- [(set_attr "type" "add,compare,compare,compare")
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+ [(set (match_dup 0)
+ (plus:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "add")
(set_attr "dot" "yes")
- (set_attr "length" "4,4,8,8")])
+ (set_attr "length" "4,8")])
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
- (match_operand:P 2 "reg_or_short_operand" ""))
+(define_insn_and_split "*add<mode>3_imm_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+ (match_operand:GPR 2 "short_cint_operand" "I,I"))
(const_int 0)))
- (set (match_operand:P 0 "gpc_reg_operand" "")
- (plus:P (match_dup 1) (match_dup 2)))]
- "reload_completed"
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (plus:GPR (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:GPR CA_REGNO))]
+ "<MODE>mode == Pmode"
+ "@
+ addic. %0,%1,%2
+ #"
+ "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
- (plus:P (match_dup 1)
- (match_dup 2)))
+ (plus:GPR (match_dup 1)
+ (match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
- "")
+ ""
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
+ (set_attr "length" "4,8")])
;; Split an add that we can't do in one insn into two insns, each of which
;; does one 16-bit part. This is used by combine. Note that the low-order
--
1.8.1.4
