Hi GCC folks, introducing a new RISC instruction set with a variable length instruction packet using a super regular extension scheme with compression techniques to separate the instruction stream into two streams, one for instructions and and one for constants:
- latest: https://metaparadigm.com/~mclark/glyph.pdf - current: https://metaparadigm.com/~mclark/glyph-20250507.pdf I am currently working on an assembler for it. I intend to come up with something that lets one manually emit constants into a .const section plus directives to tie together instructions and constants for local and global symbols, but I may also come up with a meta assembler mode that lets one use inline constants whereby the assembler splits things into streams and allocates address space for constants. I am writing a prototype assembler in Python. it hopefully should be ready in a few months. I would like to start with a Python assembler instead of using binutils because it will make for faster compression tuning when I get up to layout of the 32-bit opcodes which I intend to have contain 128-bit packed SIMD, and the 64-bit opcodes I intend to map to the 5-operand EVEX opcodes in AMD and Intel's AVX-512. this is a preview release. note: the 16-bit packet is designed as a standalone ISA, but it needs read-modify-write for bytes. we have focused on utility for function prologue and epilogue. other types and atomics will come in the 32-bit packet. it is intended to be a virtual machine target and I wish to recode AVX-512 to it. AMD and Intel can bite me if they don't want me to do this. there are interpreters in C, Python, and Go. and I also have a related project that I am working on for translation to x86. - https://github.com/michaeljclark/glyph/ - https://github.com/michaeljclark/x86/ this work has been mentioned on the RISC-V mailing list but this is the first time here. I think it is ready for early feedback. Michael.
