On 14.07.2025 20:02, Jeff Law wrote:
[...]
MD is a completely new topic to me so I am looking for some hints how
to debug the issue. Is it possible that this particular MD is not
fully complete?
Debugging failure to match is painful. I sometimes remove all the #line
markers in the generated insn-recog.cc files and follow the recognizer,
but that's only when I can't see what's going on with visual inspection
of the dumps & md file.
After spending two days I have found the source of the problem, however,
to my surprise, in completely different place:
diff --git a/gcc/config/h8300/jumpcall.md b/gcc/config/h8300/jumpcall.md
index 4e634085130..44847e4b43e 100644
--- a/gcc/config/h8300/jumpcall.md
+++ b/gcc/config/h8300/jumpcall.md
@@ -156,7 +156,7 @@ (define_insn_and_split ""
"#"
"&& reload_completed"
[(set (reg:CCZ CC_REG)
- (eq (zero_extract:HSI (match_dup 1) (const_int 1) (match_dup 2))
+ (eq:CCZ (zero_extract:HSI (match_dup 1) (const_int 1) (match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 3 [(reg:CCZ CC_REG) (const_int 0)])
Good. Note that I've got a tester I can throw things into. I'll do a
regression test of mh, ms, msx with -mint32. I can add your patch to
that tester to see what happens.
I would be nice. The new version is in the attachment. I run tests on
the simulator. Anyway, exactly the same set of test cases passes/fails
for unmodified and patched gcc.
Later I will post the patch to gcc-patches.
/J.D.
gcc/config/h8300/addsub.md | 2 +-
gcc/config/h8300/jumpcall.md | 12 ++++++------
gcc/config/h8300/testcompare.md | 26 +++++++++++++-------------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/gcc/config/h8300/addsub.md b/gcc/config/h8300/addsub.md
index 32eba9df67a..f15362594d4 100644
--- a/gcc/config/h8300/addsub.md
+++ b/gcc/config/h8300/addsub.md
@@ -271,7 +271,7 @@ (define_insn "*uaddv"
(match_operand:QHSI 2 "register_operand" "r"))
(match_dup 1)))
(set (match_operand:QHSI 0 "register_operand" "=r")
- (plus (match_dup 1) (match_dup 2)))
+ (plus:QHSI (match_dup 1) (match_dup 2)))
(clobber (reg:CC CC_REG))]
""
{
diff --git a/gcc/config/h8300/jumpcall.md b/gcc/config/h8300/jumpcall.md
index 4e634085130..44847e4b43e 100644
--- a/gcc/config/h8300/jumpcall.md
+++ b/gcc/config/h8300/jumpcall.md
@@ -156,7 +156,7 @@ (define_insn_and_split ""
"#"
"&& reload_completed"
[(set (reg:CCZ CC_REG)
- (eq (zero_extract:HSI (match_dup 1) (const_int 1) (match_dup 2))
+ (eq:CCZ (zero_extract:HSI (match_dup 1) (const_int 1) (match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 3 [(reg:CCZ CC_REG) (const_int 0)])
@@ -181,7 +181,7 @@ (define_insn_and_split ""
(lshiftrt:SI (match_dup 1) (const_int 16))))
(clobber (reg:CC CC_REG))])
(set (reg:CCZ CC_REG)
- (eq (zero_extract:SI (match_dup 4) (const_int 1) (match_dup 2))
+ (eq:CCZ (zero_extract:SI (match_dup 4) (const_int 1) (match_dup 2))
(const_int 0)))
(set (pc)
(if_then_else (match_op_dup 3 [(reg:CCZ CC_REG) (const_int 0)])
@@ -288,7 +288,7 @@ (define_expand "call"
})
(define_insn "call_insn_<mode>"
- [(call (mem:QI (match_operand 0 "call_insn_operand" "Cr"))
+ [(call (mem:QI (match_operand:P 0 "call_insn_operand" "Cr"))
(match_operand:P 1 "general_operand" "g"))]
"!SIBLING_CALL_P (insn)"
{
@@ -326,7 +326,7 @@ (define_expand "call_value"
(define_insn "call_value_insn_<mode>"
[(set (match_operand 0 "" "=r")
- (call (mem:QI (match_operand 1 "call_insn_operand" "Cr"))
+ (call (mem:QI (match_operand:P 1 "call_insn_operand" "Cr"))
(match_operand:P 2 "general_operand" "g")))]
"!SIBLING_CALL_P (insn)"
{
@@ -358,7 +358,7 @@ (define_expand "sibcall"
})
(define_insn "sibcall_insn_<mode>"
- [(call (mem:QI (match_operand 0 "call_insn_operand" "Cr"))
+ [(call (mem:QI (match_operand:P 0 "call_insn_operand" "Cr"))
(match_operand:P 1 "general_operand" "g"))]
"SIBLING_CALL_P (insn)"
{
@@ -396,7 +396,7 @@ (define_expand "sibcall_value"
(define_insn "sibcall_value_insn_<mode>"
[(set (match_operand 0 "" "=r")
- (call (mem:QI (match_operand 1 "call_insn_operand" "Cr"))
+ (call (mem:QI (match_operand:P 1 "call_insn_operand" "Cr"))
(match_operand:P 2 "general_operand" "g")))]
"SIBLING_CALL_P (insn)"
{
diff --git a/gcc/config/h8300/testcompare.md b/gcc/config/h8300/testcompare.md
index 694c9e60d4e..3b43381e64a 100644
--- a/gcc/config/h8300/testcompare.md
+++ b/gcc/config/h8300/testcompare.md
@@ -28,7 +28,7 @@
;;
(define_insn ""
[(set (reg:CCZ CC_REG)
- (eq (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
+ (eq:CCZ (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
(const_int 1)
(match_operand 1 "const_int_operand" "n"))
(const_int 0)))]
@@ -54,7 +54,7 @@ (define_insn "*tst<mode>"
(define_insn "*tsthi_upper"
[(set (reg:CCZN CC_REG)
- (compare (and:HI (match_operand:HI 0 "register_operand" "r")
+ (compare:CCZN (and:HI (match_operand:HI 0 "register_operand" "r")
(const_int -256))
(const_int 0)))]
"reload_completed"
@@ -63,7 +63,7 @@ (define_insn "*tsthi_upper"
(define_insn "*tsthi_upper_z"
[(set (reg:CCZ CC_REG)
- (compare (and:HI (match_operand:HI 0 "register_operand" "r")
+ (compare:CCZ (and:HI (match_operand:HI 0 "register_operand" "r")
(const_int -256))
(const_int 0)))]
"reload_completed"
@@ -72,7 +72,7 @@ (define_insn "*tsthi_upper_z"
(define_insn "*tstsi_upper"
[(set (reg:CCZN CC_REG)
- (compare (and:SI (match_operand:SI 0 "register_operand" "r")
+ (compare:CCZN (and:SI (match_operand:SI 0 "register_operand" "r")
(const_int -65536))
(const_int 0)))]
"reload_completed"
@@ -81,7 +81,7 @@ (define_insn "*tstsi_upper"
(define_insn "*cmp<mode>_c"
[(set (reg:CCC CC_REG)
- (ltu (match_operand:QHSI 0 "h8300_dst_operand" "rQ")
+ (ltu:CCC (match_operand:QHSI 0 "h8300_dst_operand" "rQ")
(match_operand:QHSI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{
@@ -97,7 +97,7 @@ (define_insn "*cmp<mode>_c"
(define_insn "*cmpqi_z"
[(set (reg:CCZ CC_REG)
- (eq (match_operand:QI 0 "h8300_dst_operand" "rQ")
+ (eq:CCZ (match_operand:QI 0 "h8300_dst_operand" "rQ")
(match_operand:QI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{ return "cmp.b %X1,%X0"; }
@@ -105,7 +105,7 @@ (define_insn "*cmpqi_z"
(define_insn "*cmphi_z"
[(set (reg:CCZ CC_REG)
- (eq (match_operand:HI 0 "h8300_dst_operand" "rQ")
+ (eq:CCZ (match_operand:HI 0 "h8300_dst_operand" "rQ")
(match_operand:HI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{ return "cmp.w %T1,%T0"; }
@@ -113,7 +113,7 @@ (define_insn "*cmphi_z"
(define_insn "*cmpsi_z"
[(set (reg:CCZ CC_REG)
- (eq (match_operand:SI 0 "h8300_dst_operand" "rQ")
+ (eq:CCZ (match_operand:SI 0 "h8300_dst_operand" "rQ")
(match_operand:SI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
{ return "cmp.l %S1,%S0"; }
@@ -121,7 +121,7 @@ (define_insn "*cmpsi_z"
(define_insn "*cmpqi"
[(set (reg:CC CC_REG)
- (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
+ (compare:CC (match_operand:QI 0 "h8300_dst_operand" "rQ")
(match_operand:QI 1 "h8300_src_operand" "rQi")))]
"reload_completed"
"cmp.b %X1,%X0"
@@ -129,7 +129,7 @@ (define_insn "*cmpqi"
(define_insn "*cmphi"
[(set (reg:CC CC_REG)
- (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
+ (compare:CC (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
(match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
"reload_completed"
{
@@ -150,7 +150,7 @@ (define_insn "*cmphi"
(define_insn "cmpsi"
[(set (reg:CC CC_REG)
- (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
+ (compare:CC (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
(match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
"reload_completed"
{
@@ -176,7 +176,7 @@ (define_insn "cmpsi"
(define_peephole2
[(match_scratch:QHSI 1 "r")
(set (reg:CC CC_REG)
- (compare (match_operand:QHSI 0 "memory_operand" "")
+ (compare:CC (match_operand:QHSI 0 "memory_operand" "")
(const_int 0)))]
"!mode_dependent_address_p (XEXP (operands[0], 0), MEM_ADDR_SPACE
(operands[0]))"
[(parallel [(set (reg:CCZN CC_REG) (compare:CCZN (match_dup 0) (const_int
0)))
@@ -187,7 +187,7 @@ (define_peephole2
(define_peephole2
[(match_scratch:QHSI 1 "r")
(set (reg:CC CC_REG)
- (compare (match_operand:QHSI 0 "memory_operand" "")
+ (compare:CC (match_operand:QHSI 0 "memory_operand" "")
(const_int 0)))]
"mode_dependent_address_p (XEXP (operands[0], 0), MEM_ADDR_SPACE
(operands[0]))"
[(parallel [(set (match_dup 1) (match_dup 0)) (clobber (reg:CC CC_REG))])
