Andrew Stubbs <[email protected]> writes: >> x86 gets away with >> >> (define_insn "*<avx512>_load<mode>_mask" >> [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v") >> (vec_merge:V48_AVX512VL >> (unspec:V48_AVX512VL >> [(match_operand:V48_AVX512VL 1 "memory_operand" "m")] >> UNSPEC_MASKLOAD) >> (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand" "0C") >> (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] >> >> so the (unspec ...) is wrapped around the MEM. > > I tried that; it just tried to reload the entire unspec. [...]
Out of curiosity, how did that happen? In the pattern above, the unspec is a fixed part of the pattern, whereas LRA only reloads match_operands. Perhaps the INSN_CODE pointed to a register vec_merge pattern instead? Richard
