On Fri, 27 Jun 2008 15:52:22 +0530
"Mohamed Shafi" <[EMAIL PROTECTED]> wrote:
> If the condition in the 'if' instruction is satisfied the processor
> will execute the next instruction or it will replace with a nop. So
> this means that i can instructions similar to:
>
> if eq Rx, Ry
> add Rx, Ry
> add Rx, 2
> Will it be possible to implement this in the Gcc backend ?
> Does any other targets have similar instructions?
This is very much like (a simpler version of) the ARM Thumb-2 IT
instruction. Look how config/arm/thumb2.md handles that. I think the
basic idea should be that you should define conditional instruction
patterns which emit assembly for both instructions simultaneously, e.g.
(excuse my pseudocode):
(define_insn "..."
[(...)]
"if eq Rx, Ry\;add Rx, Ry")
then there's no possibility for scheduling or other optimisations to
split the second instruction away from the first.
Julian
