On Wed, 2009-08-26 at 20:38 +0200, Paolo Bonzini wrote: > > > When I worked at AMD, I was starting to suspect that it may be more > > beneficial > > to re-enable the first schedule insns pass if you were compiling in 64-bit > > mode, since you have more registers available, and the new registers do not > > have hard wired uses, which in the past always meant a lot of spills (also, > > the > > default floating point unit is SSE instead of the x87 stack). I never got > > around to testing this before AMD and I parted company. > > Unfortunately, hardwired use of %ecx for shifts is still enough to kill > -fschedule-insns on AMD64.
The AMD64 Architecture manual I found said that various combinations of the RSI, RDI, and RCX registers are used implicitly by ten instructions or prefixes, and RBX is used by XLAT, XLATB. So it appears that there are 12 general-purpose registers available for allocation. Are 12 registers not enough, in principle, to do scheduling before register allocation? I was getting a 15% speedup on some numerical codes, as pre-scheduling spaced out the vector loads among the floating-point computations. Brad
