As I continue my work on the machine description file, I currently
worked on the bitfields again to try to get a good code generation
working. Right now, I've followed what was done in the ia64 for signed
extractions :
(define_insn "extv"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
(match_operand:DI 2 "extr_len_operand" "n")
(match_operand:DI 3 "shift_count_operand" "M")))]
""
"extr %0 = %1, %3, %2"
[(set_attr "itanium_class" "ishf")])
now this works for me except that I get for this code:
typedef struct sTest {
int64_t a:1;
int64_t b:5;
int64_t c:7;
int64_t d:15;
}STest;
int64_t bar2 (STest a)
{
int64_t res = a.d;
return res;
}
Here is what I get at the final cleanup:
;; Function bar2 (bar2)
bar2 (a)
{
short unsigned int SR.44;
short unsigned int SR.43;
short unsigned int SR.41;
short unsigned int SR.40;
short unsigned int SR.22;
short unsigned int SR.3;
<bb 2>:
SR.22 = (short unsigned int) (<unnamed-signed:15>) ((short unsigned
int) a.d & 32767);
SR.43 = SR.22 & 32767;
SR.44 = SR.43 ^ 16384;
SR.3 = (short unsigned int) (<unnamed-signed:15>) ((short unsigned
int) (<unnamed-signed:15>) (SR.44 + 49152) & 32767);
SR.40 = SR.3 & 32767;
SR.41 = SR.40 ^ 16384;
return (int64_t) (<unnamed-signed:15>) (SR.41 + 49152);
}
I don't understand why I get all these instructions. I know that
because it's signed, it is more complicated but I would prefer to get
an unsigned extract and the a shift left/shift right. Thus 3
instructions.
Right now, I get so many more instructions that represent what I
showed from the final cleanup.
Any reason for all these instructions or ideas on how to get to my 3
instructions ?
Thank you for your help and time,
Jean Christophe Beyler
