Hi, On Mon, 17 May 2010, Ian Lance Taylor wrote:
> >> Since the atomic operations are being built into the compiler, the > >> intent is to eventually optimize and inline them for speed... and in > >> the best case, simply result in a load or store. That's further work > >> of course, but these options are laying some of the groundwork. > > > > Are you and the other proponents of that memory model seriously > > proposing it as an alternative to explicit locking via atomic builtins > > (that map to some form of atomic instructions)? > > I'm not sure what you mean here. Do you an alternative way to > implement the C++0x proposed standard? I actually see no way to implement the proposed memory model on common hardware, except by emitting locked instructions and memory barriers for all memory accesses to potentially shared (and hence all non-stack) data. And even then it only works on a subset of types, namely those for this the hardware provides such instructions with the associated guarantees. > Or are you questioning the approach taken by the standard? I do, yes. Ciao, Michael.
