Hello all,
I am trying to port GCC 4.5.1 for a processor that has the following
addressing capability:
The data memory address space of 64K bytes is represented by a total
of 15 bits, with each address selecting a 16-bit element. When using
the address register, the LSB of address reg (AD) points to a 16-bit
field in data memory. If a data memory line is 128 bits there are 8,
16-bit elements per data memory line. We use little endian addressing,
so
if AD=0, bits [15:0] of data memory line address 0 would be selected.
If AD=1, bits [31:16] of data memory line address 0 would be selected.
If AD=9, bits [31:16] of data memory line address 1 would be selected.
So if i have the following program
short arr[5] = {11,12,13,14,15};
int foo ()
{
short a = arr[0] + arr[3];
return a;
}
Assume that short is 16bits and short address is 2byte aligned.Then I
expect the following code to get generated:
mov a0,#arr // Load the address
mov a1, a0 // Copy the address
add a1, 1 // Increment the location by 1 so that the address
points to arr[1]
ld.16 g0, (a1) // Load the value 12 into g0
mov a1, a0 // Copy the address
add a1, 3 // Increment the location by 3 so that the address
points to arr[3]
ld.16 g1, (a1) // Load the value 14 into g0
add g1, g1, g0 // Add 12 and 14
For the following code:
short arr[5] = {11,12,13,14,15};
int foo ()
{
short a,b;
a = (short) (&arr[3] - &arr[1]); // a is 2 after this operation
b = (short) ((char*)&arr[3] - (char*)&arr[1]); // b is 4 after this operation
return a;
}
My question is should i set the macro BITS_PER_UNIT = 16 to get a code
generated like this? From IRC chat i realize that BITS_PER_UNIT != 8
is seriously rotten. If that is the case how can i proceed to port
this target?
Regards,
Shafi
