Question about alias check in ddg.c

[Revital1 Eres]

Hello,

When trying to compile the following loop with GCC -r164298 with modulo
scheduling pass enabled on PowerPC I get that the inter loop edges
between the memory instructions are created in the DDG although the
following check in ddg.c exists:

static void
add_inter_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
{
  if (!insns_may_alias_p (from->insn, to->insn))
     return;

With GCC -r146278 the edges are not created in the DDG.
Looking more closely into the code I see the following differences in ddg.c
between the GCC versions:

The new version of GCC contains:

add_inter_loop_mem_dep ()  -> ...-> may_alias_p()

while with GCC -r146278:

add_inter_loop_mem_dep () -> ... -> insn_alias_sets_conflict_p()

I do not understand this behavior and I appreciate an explanation.

Thanks,
Revital


void foo( int * __restrict__ dst,  int * __restrict__ src1,
                  int * __restrict__ src2)
{
    int x, y;

   for( x = 0; x < 100; x+=1 )
        {
            dst[x] = ( src1[x] * src2[x] ) ;
        }
}