I had already removed all define_delay definitions in mips.md.
There were still a few leftover branches that had nop in the delay slot.
One of these cases is the first example I showed.
I solved the issue by editing the SETUP_GTX macro located in
glibc-2.3.6/sysdeps/mips/sys/asm.h
The macro was:
.set noreorder;
move r, $31; /* Save old ra.*/
bal 10f; /* Find addr of cpload./
nop;
10:
.cpload $31;
move $31, r;
.set reorder
So I simply removed the nop after the bal instruction. The .cpload function
expects the PC of label 10 in the $ra address. Since I am storing
the PC of the first instruction of .cpload into $ra (the instruction after
bal),
then .cpload still functions correctly.
-Brandon
On 02/18/2011 01:43 AM, Ian Lance Taylor wrote:
"Brandon H. Dwiel"<bhdw...@ncsu.edu> writes:
I would like to make the changes necessary so that the compiler expects the PC
of the
instruction directly after the branch to be put in the $ra register.
I cannot locate where it is specified that PC+8 of an "and link" instruction is
to
be put in the $ra so that I may change it.
It's not specified in that way. Instead, it's specified that jalr has a
delay slot. See the uses of define_delay in gcc/config/mips/mips.md.
Ian
