On 07/20/2011 04:55 AM, Richard Sandiford wrote: > The "loc_result &&" check makes it seem as though we're trying to cope > with cases XVECLEN is zero, but that only works if the first (dead) load > of XEXVECP (regs, 0, 0) is optimised away. Is a length of 0 valid > in this context? If not, should we assert for it?
I don't believe a zero length is valid. An assert would be ok. > Also, is the size assignment in the loop supposed to always read > element 0, or is it a typo for XVECEXP (regs, 0, i)? That sure looks like a typo. Though I suspect the usual case has N registers of the same mode, so we didn't notice. r~
