Hi all, The latest errata for Texas Instruments' Cortex-M3 family, updated last October [1], contains a disturbing new problem triggered by non-word-aligned writes to SRAM. This is the kind of errata that is effectively addressed with a compiler work-around. FWIW, it has already been addressed by a popular commercial toolchain vendor [2]. I was wondering if the GCC ARM maintainers were aware of this bug, and if somebody implemented or was working on a compiler work-around for this problem. I had a look at recent discussions and patches on the GCC mailing lists, but could not find anything. I'm looking for something along the lines of the -mfix-cortex-m3-ldrd fix, but for that new alignment write erratum.
[1] http://www.ti.com/lit/er/spmz642b/spmz642b.pdf [2] http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/iccarm.ENU.html Thanks for your attention, LP Brais
