On Fri, Dec 6, 2013 at 12:41 AM, BELBACHIR Selim <selim.belbac...@fr.thalesgroup.com> wrote: > Hum, I can't change gcc branch because I'm tighted to gnat 7.1.2 based on gcc > 4.7.3 (I saw that LRA was merged in 4.8). I will use a workaround for the > moment (i.e. disable wide offset MEM on conditional moves). > Does someone know if gnat frontend will rebase on 4.8 soon :) ? (or maybe LRA > will be merged in 4.7.4 ?)
If this is the Ada front-end, then it is already part of 4.8 release. Or is this some other front-end? Thanks, Andrew Pinski > > Thanks > > Selim > > -----Message d'origine----- > De : Jeff Law [mailto:l...@redhat.com] > Envoyé : mercredi 4 décembre 2013 18:02 > À : BELBACHIR Selim; gcc@gcc.gnu.org > Objet : Re: Controling reloads of movsicc pattern > > On 12/04/13 03:22, BELBACHIR Selim wrote: >> Hi, >> >> My target has : >> - 2 registers class to store SImode (like m68k, data $D & address $A). >> - moves from wide offset MEM to $D or $A (ex: mov d($A1+50),$A2 or >> mov d($A1+50),$D1) >> - conditional moves from offset MEM to $D or $A but with a restriction : >> offset MEM conditionally moved to $A has a limited offset of >> 0 or 1 (ex: mov.ifEQ d($A1,1),$A1 whereas we can still do mov.ifEQ >> d($A1,50),$D1) >> >> The predicate of movsicc pattern tells GCC that wide offset MEM is allowed >> and constraints describe 2 alternatives for 'wide offset MEM -> $D ' and >> 'restricted offset MEM -> $A" : >> >> (define_insn_and_split "movsicc_internal" >> [(set (match_operand:SI 0 "register_operand" "=a,d,m,a,d,m,a,d,m") >> (if_then_else:SI >> (match_operator 1 "prism_comparison_operator" >> [(match_operand 4 "cc_register" "") (const_int 0)]) >> (match_operand:SI 2 "nonimmediate_operand" " >> v,m,r,0,0,0,v,m,r") ;; "v" constraint is for restricted offset MEM >> (match_operand:SI 3 " nonimmediate_operand" " >> 0,0,0,v,m,r,v,m,r")))] ;; the last 3 alternatives are split to match >> the other alternatives >> >> >> >> I encountered : (on gcc4.7.3) >> >> core_main.c:354:1: error: insn does not satisfy its constraints: >> (insn 1176 1175 337 26 (set (reg:SI 5 $A5) >> (if_then_else:SI (ne (reg:CC 56 $CCI) >> (const_int 0 [0])) >> (mem/c:SI (plus:SI (reg/f:SI 0 $A0) >> (const_int 2104 [0x838])) [9 %sfp+2104 S4 A32]) >> (const_int 1 [0x1]))) core_main.c:211:32 158 >> {movsicc_internal} >> >> Due to reload pass (core_main.c.199r.reload). >> >> >> How can I tune reload or write my movsicc pattern to prevent reload pass >> from generating a conditional move from wide offset MEM to $A registers ?? > If at all possible, I would recommend switching to LRA. There's an up-front > cost, but it's definitely the direction all ports should be heading. > Avoiding reload is, umm, good. > > jeff >
